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    DEEP TRENCH CONTACT AND ISOLATION OF BURIED PHOTODETECTORS
    1.
    发明申请
    DEEP TRENCH CONTACT AND ISOLATION OF BURIED PHOTODETECTORS 失效
    DEEP TRENCH接触和分离的BEDIED光电子

    公开(公告)号：US20070102740A1

    公开(公告)日：2007-05-10

    申请号：US11164098

    申请日：2005-11-10

    申请人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Jeffrey Johnson ,  Jerome Lasky

    发明人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Jeffrey Johnson ,  Jerome Lasky

    IPC分类号： H01L31/113

    CPC分类号： H01L27/14647 ,  H01L27/14603 ,  H01L27/14634

    摘要： The invention provides vertically-stacked photodiodes buried in a semiconductor material that are isolated and selectively contacted by deep trenches. One embodiment of the invention provides a pixel sensor comprising: a plurality of photosensitive elements formed in a substrate, each photosensitive element being adapted to generate photocharges in response to electromagnetic radiation; and a plurality of photocharge transfer devices, each photocharge transfer device being coupled to at least one of the plurality of photosensitive elements.

    摘要翻译： 本发明提供了埋藏在半导体材料中的垂直堆叠的光电二极管，其被深沟槽隔离并选择性地接触。 本发明的一个实施例提供了一种像素传感器，包括：形成在基板中的多个感光元件，每个光敏元件适于响应于电磁辐射产生光电荷; 以及多个光电荷转移装置，每个光电荷转移装置耦合到所述多个感光元件中的至少一个。

    RECESSED GATE FOR A CMOS IMAGE SENSOR
    4.
    发明申请
    RECESSED GATE FOR A CMOS IMAGE SENSOR 有权
    CMOS图像传感器的接收门

    公开(公告)号：US20070184614A1

    公开(公告)日：2007-08-09

    申请号：US11735223

    申请日：2007-04-13

    申请人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jerome Lasky

    发明人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jerome Lasky

    IPC分类号： H01L21/336

    CPC分类号： H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

    摘要： A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.

    摘要翻译： 一种新颖的CMOS图像传感器单元结构及其制造方法。 成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层 栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道 收集阱层和扩散区域之间的区域。 栅极导体的底部的一部分在衬底的表面下方凹进。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

    RECESSED GATE FOR AN IMAGE SENSOR
    5.
    发明申请
    RECESSED GATE FOR AN IMAGE SENSOR 有权
    图像传感器的门

    公开(公告)号：US20060124976A1

    公开(公告)日：2006-06-15

    申请号：US10905097

    申请日：2004-12-15

    申请人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jerome Lasky

    发明人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jerome Lasky

    IPC分类号： H01L31/113 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

    摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

    摘要翻译： 一种新颖的图像传感器单元结构及其制造方法。 成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层 在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区 。 栅极导体底部的一部分凹陷在基板的表面下方。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

    METHOD AND STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF
    6.
    发明申请
    METHOD AND STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF 有权
    集成电路制造过程中充电放电的方法与结构及其分离

    公开(公告)号：US20070013072A1

    公开(公告)日：2007-01-18

    申请号：US11160468

    申请日：2005-06-24

    申请人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Sullivan ,  Steven Voldman

    发明人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Sullivan ,  Steven Voldman

    IPC分类号： H01L23/52

    CPC分类号： H01L27/0248 ,  Y10S438/926

    摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

    摘要翻译： 一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。 该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

    IMAGE SENSOR CELLS
    8.
    发明申请
    IMAGE SENSOR CELLS 有权
    图像传感器细胞

    公开(公告)号：US20060186505A1

    公开(公告)日：2006-08-24

    申请号：US10906510

    申请日：2005-02-23

    申请人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

    发明人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

    IPC分类号： H01L31/06

    CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

    摘要： A structure (and method for forming the same) for an image sensor cell. The structure includes (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in direct physical contact with the charge collection well, the surface pinning layer comprising a semiconductor material doped with a second doping polarity opposite to the first doping polarity; and (d) an electrically conducting push electrode being in direct physical contact with the surface pinning layer but not being in direct physical contact with the charge collection well.

    摘要翻译： 用于图像传感器单元的结构（及其形成方法）。 该结构包括（a）半导体衬底; （b）在所述衬底上的电荷收集阱，所述电荷收集阱包括掺杂有第一掺杂极性的半导体材料; （c）与电荷收集阱直接物理接触的表面钉扎层，所述表面钉扎层包括掺杂有与第一掺杂极性相反的第二掺杂极性的半导体材料; 和（d）与表面钉扎层直接物理接触但不与电荷收集阱直接物理接触的导电推动电极。

    IMAGE SENSOR CELLS
    9.
    发明申请
    IMAGE SENSOR CELLS 失效
    图像传感器细胞

    公开(公告)号：US20070108485A1

    公开(公告)日：2007-05-17

    申请号：US11619024

    申请日：2007-01-02

    申请人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

    发明人： James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Richard Rassel

    IPC分类号： H01L31/113 ,  H01L21/00

    CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

    摘要： A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.

    摘要翻译： 用于图像传感器单元的结构（及其形成方法）。 该方法包括提供半导体衬底。 然后，在半导体衬底中形成电荷收集阱，电荷收集阱包含第一掺杂极性的掺杂剂。 接下来，在电荷收集阱中形成表面钉扎层，表面钉扎层包括与第一掺杂极性相反的第二掺杂极性的掺杂剂。 然后，导电的推动电极形成为与表面钉扎层直接物理接触，但不与电荷收集阱直接物理接触。 然后，在半导体衬底上形成传输晶体管。 传输晶体管包括第一和第二源极/漏极区域和沟道区域。 第一和第二源/漏区包括第一掺杂极性的掺杂剂。 第一源极/漏极区域与电荷收集阱直接物理接触。

    STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES
    10.
    发明申请
    STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
    用于收集电子和孔的像素传感器单元的结构

    公开(公告)号：US20070296006A1

    公开(公告)日：2007-12-27

    申请号：US11850776

    申请日：2007-09-06

    申请人： James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jeffrey Johnson ,  Alain Loiseau

    发明人： James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jeffrey Johnson ,  Alain Loiseau

    IPC分类号： H01L31/00

    CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281 ,  H01L31/1037

    摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

    摘要翻译： 本发明涉及一种像素传感器单元的设计结构。 像素传感器单元对于给定的光量大约使可用信号加倍。 具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上​​，以及p型收集阱区域 用于收集由撞击光子产生的孔的基板的表面。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。