公开(公告)号：US08476947B2

公开(公告)日：2013-07-02

申请号：US13295875

申请日：2011-11-14

申请人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

公开(公告)号：US20130120044A1

公开(公告)日：2013-05-16

申请号：US13295875

申请日：2011-11-14

申请人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

摘要翻译： 提供了具有时钟发生和分配电路的集成电路。 集成电路可以包括被配置为生成作为彼此的延迟版本的多个时钟信号的锁相环。 时钟信号可以使用串行连接的时钟缓冲器块分布到集成电路上的各个区域。 每个缓冲块可以包括并联耦合的双向缓冲电路对。 每个缓冲电路可以具有被配置为接收输入时钟信号的第一输入，提供输入时钟信号的校正版本的输出（例如，提供具有期望的占空比的输出时钟信号的输出）， 第二输入端，接收用于设定所述输出时钟信号的期望占空比的第一延迟时钟信号;以及第三输入端，其接收至少当所述第一延迟时钟信号上升时为高的第二延迟时钟信号。

公开(公告)号：US08760328B1

公开(公告)日：2014-06-24

申请号：US13620126

申请日：2012-09-14

申请人： Wei Yee Koay ,  Chin Ghee Ch'ng ,  Ket Chiew Sia ,  Tony Ngai ,  Sean Woei Voon

发明人： Wei Yee Koay ,  Chin Ghee Ch'ng ,  Ket Chiew Sia ,  Tony Ngai ,  Sean Woei Voon

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.

摘要翻译： 集成电路系统可以包括第一集成电路（IC），第二IC和接口电路。 第一IC可操作以以第一数据速率输出并行数据流。 第二IC可操作地以第二日期速率输出串行数据流。 第二数据速率可能不同于第一数据速率。 接口电路可以耦合在第一集成电路和第二集成电路之间。 接口电路可以用于将从第一IC接收的并行数据流转换成具有第二数据速率的串行数据流。 接口电路还可以用于将从第二IC接收的串行数据流转换成具有第一数据速率的并行数据流。

公开(公告)号：US07855577B1

公开(公告)日：2010-12-21

申请号：US12269149

申请日：2008-11-12

申请人： Chai Yee Teng ,  Ket Chiew Sia

发明人： Chai Yee Teng ,  Ket Chiew Sia

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/018514 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/018585

摘要： A buffer circuit for using one buffer for multiple differential I/O standards is disclosed. The buffer circuit includes a differential input buffer. The first input of the differential input buffer may receive an input and the second input is coupled to a switch. The switch may be a one-time-programmable switch. The switch has a coupling to transmit a signal to the second input of the differential input buffer. The switch may be programmed to selectively transmit different signals to the differential input buffer. The first input terminal of the switch may receive an inverted version of the input signal and the second input terminal of the switch may receive a reference voltage. The buffer may transmit an LVDS signal or an SSTL signal or an HSTL signal. Using one differential buffer for multiple I/O standards may reduce the overall die size and may save space on the die.

摘要翻译： 公开了一种用于使用一个缓冲器用于多个差分I / O标准的缓冲电路。 缓冲电路包括差分输入缓冲器。 差分输入缓冲器的第一输入可以接收输入，第二输入耦合到开关。 开关可以是一次性可编程开关。 开关具有将信号传输到差分输入缓冲器的第二输入的耦合。 该开关可被编程为选择性地向差分输入缓冲器发送不同的信号。 开关的第一输入端子可以接收输入信号的反相形式，并且开关的第二输入端子可以接收参考电压。 缓冲器可以发送LVDS信号或SSTL信号或HSTL信号。 对于多个I / O标准使用一个差分缓冲器可能会降低整体管芯尺寸，并且可以节省管芯上的空间。

公开(公告)号：US08723575B1

公开(公告)日：2014-05-13

申请号：US13554293

申请日：2012-07-20

申请人： Ee Mei Ooi ,  Kin Hong Au ,  Ket Chiew Sia ,  Yan Chong ,  Joseph Huang

发明人： Ee Mei Ooi ,  Kin Hong Au ,  Ket Chiew Sia ,  Yan Chong ,  Joseph Huang

IPC分类号： H03H11/26

CPC分类号： H03H11/265

摘要： An integrated circuit may include a delay circuit that receives an input signal at a first logic level and produces a delayed output signal at a second logic level at an output terminal. The integrated circuit may include a preset circuit coupled to the delay circuit. The preset circuit may receive the input signal and pre-drive the delayed output signal to an intermediate logic level that lies between the first and second logic levels.

摘要翻译： 集成电路可以包括延迟电路，其以第一逻辑电平接收输入信号，并在输出端产生处于第二逻辑电平的延迟的输出信号。 集成电路可以包括耦合到延迟电路的预设电路。 预置电路可以接收输入信号并将延迟的输出信号预驱动到位于第一和第二逻辑电平之间的中间逻辑电平。

公开(公告)号：US08686758B1

公开(公告)日：2014-04-01

申请号：US12423777

申请日：2009-04-14

申请人： Ket Chiew Sia ,  Choong Kit Wong ,  Boon Jin Ang

发明人： Ket Chiew Sia ,  Choong Kit Wong ,  Boon Jin Ang

IPC分类号： H03B1/00 ,  H03K3/00 ,  H03K17/56 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K19/018585 ,  H03K17/102 ,  H03K17/122 ,  H03K19/018521

摘要： I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.

摘要翻译： 公开了I / O电路和用于发送不同类型的I / O信号的方法。 I / O电路的实施例包括具有耦合到晶体管的多个开关的多个晶体管。 开关可用于选择性地将晶体管耦合到电源或另一晶体管以形成不同的晶体管配置。 晶体管可以被配置为形成并行配置或堆叠配置。 堆叠晶体管可以减小晶体管中的电压摆幅并随后减小晶体管的劣化。

公开(公告)号：US08570064B1

公开(公告)日：2013-10-29

申请号：US13294741

申请日：2011-11-11

申请人： Foong Tek Chan ,  Ket Chiew Sia

发明人： Foong Tek Chan ,  Ket Chiew Sia

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/018578 ,  H03K19/0005 ,  H03K19/018585 ,  H04L25/0278

摘要： Methods, circuits, and systems for termination calibration are provided. Differential input buffer circuitry is used to compare a signal level at an input/output pad and a first reference signal level. Control circuitry is used to control a controllably variable impedance based on the output of the differential input buffer circuitry. Optionally, second differential input buffer circuitry is used to compare the signal level at the input/output pad to a second reference signal level. The control circuitry is used to control the controllably variable impedance based on the output of both the first and the second differential input buffer circuitry.

摘要翻译： 提供了终端校准的方法，电路和系统。 差分输入缓冲电路用于比较输入/输出焊盘的信号电平和第一参考信号电平。 控制电路用于基于差分输入缓冲器电路的输出来控制可控制的可变阻抗。 可选地，第二差分输入缓冲器电路用于将输入/输出焊盘处的信号电平与第二参考信号电平进行比较。 控制电路用于基于第一和第二差分输入缓冲器电路的输出来控制可控制的可变阻抗。

公开(公告)号：US08327305B1

公开(公告)日：2012-12-04

申请号：US12534053

申请日：2009-07-31

申请人： Woi Jie Hooi ,  Teik Wah Lim ,  Ket Chiew Sia

发明人： Woi Jie Hooi ,  Teik Wah Lim ,  Ket Chiew Sia

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.

摘要翻译： 公开了一种将电路块放置在集成电路（IC）上的电路和方法。 所公开方法的实施例包括基于预定值将IC划分成多个区域。 该预定值可以是在IC上的特定区域上测量的电压降值。 电路块的性能要求被确定并放置在IC的一个区域中。 在一个实施例中，电路块的放置基于IC上的特定区域的性能要求和测量值。 测量值可以是电压降值，并且具有较高性能的电路块可以放置在具有较低电压降值的区域中。

公开(公告)号：US07180329B1

公开(公告)日：2007-02-20

申请号：US11111352

申请日：2005-04-20

申请人： Ket Chiew Sia ,  Choong Kit Wong ,  Boon Haw Ooi ,  Kok Siong Tee

发明人： Ket Chiew Sia ,  Choong Kit Wong ,  Boon Haw Ooi ,  Kok Siong Tee

IPC分类号： H03K19/0175

CPC分类号： H03K3/013 ,  H03K3/356113

摘要： An adjustable level shifter with native and kicker transistors is provided. The level shifter provides high switching speeds, adjustable output voltage levels, and low jitter. The level shifter has first and second thick-oxide p-channel metal-oxide-semiconductor (PMOS) transistors, first and second thick-oxide native n-channel metal-oxide-semiconductor (NMOS) transistors, and first and second thin-oxide NMOS transistors. The first PMOS transistor, first native transistor, and first NMOS transistor are connected in series and the second PMOS transistor, second native transistor, and second NMOS transistor are connected in series. An input data signal and an inverted version of the input data signal drive the gates of the thin-oxide NMOS transistors. A node located between the first PMOS transistor and first native transistor is connected to an output data terminal. The kicker transistor is connected in parallel with the first PMOS transistor.

摘要翻译： 提供了具有原始和踢击晶体管的可调电平移位器。 电平转换器提供高开关速度，可调节的输出电压电平和低抖动。 电平移位器具有第一和第二厚氧化物p沟道金属氧化物半导体（PMOS）晶体管，第一和第二厚氧化物本征n沟道金属氧化物半导体（NMOS）晶体管，以及第一和第二薄氧化物 NMOS晶体管。 第一PMOS晶体管，第一天体晶体管和第一NMOS晶体管串联连接，第二PMOS晶体管，第二天体晶体管和第二NMOS晶体管串联连接。 输入数据信号和反相版本的输入数据信号驱动薄氧化物NMOS晶体管的栅极。 位于第一PMOS晶体管和第一天然晶体管之间的节点连接到输出数据端。 该激光晶体管与第一PMOS晶体管并联连接。