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9 条记录 (耗时 0.036 秒)

    Sub-ranging A/D converter with improved error correction
    1.
    发明授权
    Sub-ranging A/D converter with improved error correction 失效
    子范围A / D转换器，具有改进的纠错

    公开(公告)号：US4804960A

    公开(公告)日：1989-02-14

    申请号：US106714

    申请日：1987-10-08

    申请人： John W. Fernandes ,  Gerald A. Miller ,  Andrew M. Mallinson ,  Stephen R. Lewis

    发明人： John W. Fernandes ,  Gerald A. Miller ,  Andrew M. Mallinson ,  Stephen R. Lewis

    IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/34

    CPC分类号： H03M1/0695 ,  H03M1/0682 ,  H03M1/162 ,  H03M1/363

    摘要： A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 5th cycle making possible a 14-bit output or an increased yield of 12-bit converters.

    摘要翻译： 一个12位子范围A / D转换器，通过四个连续的子测距周期操作，周期之间的增益为8：1。 每个周期的残留信号指向一个四位闪存转换器，其输出为DAC的相应位电流源设置锁存器。 闪存转换器输入电路包括相同的残留和参考放大器，驱动对称的残留和参考网络，用于控制闪存转换器比较器。 将每个周期的DAC输出与模拟输入信号进行比较，以产生相应的新的残留信号。 有15个位电流源，第一个周期有三个，最后三个周期中有四个。 每组4位电流源的MSB是具有与前一组的LSB相同的当前权重的重叠位。 重叠位的设置使得可以在第2到第4个周期的每一个周期内为DAC开发正确的输出，而不改变在先前周期中已经确定的位。 该转换器提供可选的第5个周期，使得14位输出或增加的12位转换器的产量成为可能。

    Sub-ranging A/D converter with flash converter having balanced input
    2.
    发明授权
    Sub-ranging A/D converter with flash converter having balanced input 失效
    具有平衡输入的带闪存转换器的子范围A / D转换器

    公开(公告)号：US4814767A

    公开(公告)日：1989-03-21

    申请号：US106712

    申请日：1987-10-08

    申请人： John W. Fernandes ,  Gerald A. Miller ,  Andrew M. Mallinson

    发明人： John W. Fernandes ,  Gerald A. Miller ,  Andrew M. Mallinson

    IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/34

    CPC分类号： H03M1/0695 ,  H03M1/0682 ,  H03M1/162 ,  H03M1/363

    摘要： A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 5th cycle making possible a 14-bit output or an increased yield of 12-bit converters.

    High frequency diffusion muffler for gas jets
    4.
    发明授权
    High frequency diffusion muffler for gas jets 失效
    用于气体射流的高频扩散消声器

    公开(公告)号：US4109756A

    公开(公告)日：1978-08-29

    申请号：US742726

    申请日：1976-11-17

    申请人： Gerald A. Miller ,  John M. Zabsky

    发明人： Gerald A. Miller ,  John M. Zabsky

    IPC分类号： F01N1/10 ,  F16L55/027 ,  F01N1/08

    CPC分类号： F16L55/02781

    摘要： A dissipative-type muffler for attenuating the high velocity discharge of a high pressure-high temperature safety valve. A path of flow constituting four stages of controlled turbulence suppressed diffusion is formed internally of the muffler extending from an intake into a plenum chamber then distributed past a plurality of parallel arranged radial diffuser flanges and an acoustical liner before exiting to atmosphere at relatively low velocity and low noise level. Laminar flow to small scale turbulence is obtained in the first stage by a jet impingement directional reversal in a controlled spacing discharge from an intake pipe within the plenum chamber. In the second stage, small scale discharge turbulence of high frequency is achieved by laminar flow induced via radial diffusion through controlled gap spacings between the diffuser flanges. Buffer plate impingement of the second stage discharge is then effected in the third stage after which high frequency noise attenuation by means of an acoustical composition is obtained in the fourth stage before exiting to atmosphere.

    摘要翻译： 一种用于衰减高压高温安全阀的高速放电的耗散型消声器。 在消声器的内部形成一个形成控制湍流抑制扩散的流动路径，该消声器从进气口延伸到通风室中，然后分布在多个平行布置的径向扩散器凸缘和隔音衬垫之前，以相对较低的速度离开大气， 低噪音水平 在第一阶段通过喷气冲击方向反转获得在小型湍流中的层流，从而与增压室内的进气管相接触的间隔排放。 在第二阶段，通过在扩散器法兰之间的可控间隙间隔通过径向扩散引起的层流实现了高频率的小规模放电湍流。 然后在第三阶段进行第二级放电的缓冲板冲击，之后在离开大气之前在第四阶段获得借助于声学组合物的高频噪声衰减。

    Jitter and load insensitive charge transfer
    6.
    发明授权
    Jitter and load insensitive charge transfer 有权
    抖动和负载不敏感的电荷转移

    公开(公告)号：US06452531B1

    公开(公告)日：2002-09-17

    申请号：US09385211

    申请日：1999-08-27

    申请人： Gerald A. Miller ,  Michael C. W. Coln

    发明人： Gerald A. Miller ,  Michael C. W. Coln

    IPC分类号： H03M112

    CPC分类号： H03M3/464

    摘要： Methods and apparatus for jitter and load insensitive charge transfer are disclosed. A quantity of charge is transferred to or from a load during a transfer interval, wherein the charge transferred is significantly insensitive to load characteristics and variations in the transfer interval. A succession of identical or different quantities of charge may be transferred to or from the load during successive transfer intervals. The charge transfer circuit may be employed in mixed switched/continuous-time circuit configurations, and in particular may be used as a unipolar or bipolar one-bit digital-to-analog converter to provide quantized feedback in a sigma-delta analog-to-digital converter circuit configuration. The charge transfer circuit avoids problems of integrating amplifier nonlinearity and input signal distortion in such sigma-delta analog-to-digital converter circuits, and facilitates monolithic fabrication of sigma-delta analog-to-digital converters using standard integrated circuit fabrication techniques.

    摘要翻译： 公开了抖动和负载不敏感电荷转移的方法和装置。 在传送间隔期间，一定量的电荷被传送到负载，其中转移的电荷对负载特性和转移间隔的变化显着不敏感。 在连续的传送间隔期间，可以将相同或不同数量的电荷的连续传递到负载或从负载传送。 电荷转移电路可以用于混合开关/连续时间电路配置，并且特别地可以用作单极或双极的一位数模转换器，以在Σ-Δ模拟 - 数模转换器中提供量化反馈， 数字转换器电路配置。 电荷转移电路避免了在这种Σ-Δ模数转换器电路中集成放大器非线性和输入信号失真的问题，并且使用标准集成电路制造技术促进了Σ-Δ模数转换器的单片制造。

    Sample/hold amplifier for integrated circuits
    7.
    发明授权
    Sample/hold amplifier for integrated circuits 失效
    用于集成电路的采样/保持放大器

    公开(公告)号：US4833345A

    公开(公告)日：1989-05-23

    申请号：US151914

    申请日：1988-02-03

    申请人： Gerald A. Miller

    发明人： Gerald A. Miller

    IPC分类号： G11C27/02

    CPC分类号： G11C27/026

    摘要： A sample/hold amplifier comprising two transconductance stages with their inverting input terminals connected together. In sample mode, the input signal is connected to the non-inverting input of the first stage, and a hold capacitor is connected to the non-inverting input terminal of the second stage and driven by the amplifier output through a feedback circuit which forces the hold capacitor voltage to track the input signal. Upon switchover to hold mold, the roles of the two transconductance stages are interchanged: The non-inverting input terminal of the first stage is connected through a feedback circuit to the amplifier output, and the second stage receives as an input signal the voltage of the hold capacitor, which now is disconnected from the amplifier output. The net offset voltage developed on the hold capacitor is the difference between the respective offsets of the two transconductance stages. This net offset voltage is compensated for by an equal and opposite voltage in hold mode, due to the interchange of roles of the two transconductance stages.

    摘要翻译： 一个采样/保持放大器，包括两个跨导级，其反相输入端连接在一起。 在采样模式下，输入信号连接到第一级的同相输入，保持电容连接到第二级的非反相输入端，并通过反馈电路由放大器输出驱动，该反馈电路迫使 保持电容电压跟踪输入信号。 切换到保持模式时，两个跨导级的作用互换：第一级的非反相输入端通过反馈电路连接到放大器输出，第二级接收输入信号的电压 保持电容器，其现在与放大器输出断开。 在保持电容器上产生的净偏移电压是两个跨导级的相应偏移之间的差。 由于两个跨导级的作用相互交换，这种净偏移电压在保持模式下被相等和相反的电压补偿。