公开(公告)号：US06201253B1

公开(公告)日：2001-03-13

申请号：US09177335

申请日：1998-10-22

Applicant: Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

Inventor： Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

IPC: G01N2186

CPC classification number: B24B37/013 ,  B24B49/04 ,  B24B49/12 ,  H01L21/67253

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract translation: 利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。 该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。 该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。 此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。 还公开了一种用于抛光半导体晶片的第一侧的装置。

公开(公告)号：US5559733A

公开(公告)日：1996-09-24

申请号：US482765

申请日：1995-06-07

Applicant: Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

Inventor： Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

IPC: G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/22 ,  G11C11/223

Abstract: A ferroelectric memory includes a constant voltage source, a capacitor having first and second electrodes, and a transistor having a gate. A switch alternately connects the gate of the transistor to the first electrode and the constant voltage source. In another embodiment, there are two ferroelectric transistors, and the first electrode of each capacitor is connected both to the gate of the transistor and to a voltage source external of the memory.

Abstract translation: 铁电存储器包括恒压源，具有第一和第二电极的电容器和具有栅极的晶体管。 开关将晶体管的栅极交替地连接到第一电极和恒定电压源。 在另一实施例中，存在两个铁电晶体管，并且每个电容器的第一电极都连接到晶体管的栅极和存储器外部的电压源。

公开(公告)号：US06354908B2

公开(公告)日：2002-03-12

申请号：US09754429

申请日：2001-01-04

Applicant: Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

Inventor： Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

IPC: B24B4900

CPC classification number: B24B37/013 ,  B24B49/04 ,  B24B49/12 ,  H01L21/67253

Abstract: A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

Abstract translation: 利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。 该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。 该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。 此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。 还公开了一种用于抛光半导体晶片的第一侧的装置。

公开(公告)号：US06316276B1

公开(公告)日：2001-11-13

申请号：US09213803

申请日：1998-12-17

Applicant: John W. Gregory ,  Derryl D. J. Allman

Inventor： John W. Gregory ,  Derryl D. J. Allman

IPC: H01L2100

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/763

Abstract: A method of planarizing a semiconductor that includes (i) a substrate material, (ii) a first reflective substance positioned on the substrate material, (iii) an intermediate material positioned on the first reflective substance, wherein a channel is defined in a structure which includes the substrate, the first reflective substance, and the intermediate material, and (iv) a second reflective substance positioned on the intermediate material and in the channel is disclosed. The method includes the steps of (i) directing light onto a first side of the semiconductor wafer, (ii) polishing the first side of the semiconductor wafer in order to remove matter therefrom and expose the first reflective substance, the matter including the second reflective substance and the intermediate material, (iii) detecting when light directed in the directing step is simultaneously reflected by (A) the first reflective substance positioned on the substrate, and (B) the second reflective substance positioned in the channel, and generating an endpoint detection signal in response thereto, and (iv) terminating the polishing step in response to generation of the endpoint detection signal. An associated apparatus is also disclosed.

Abstract translation: 一种平面化半导体的方法，包括：（i）衬底材料，（ii）位于衬底材料上的第一反射物质，（iii）位于第一反射物质上的中间材料，其中通道被限定在 包括基板，第一反射物质和中间材料，以及（iv）位于中间材料和通道中的第二反射物质。 该方法包括以下步骤：（i）将光引导到半导体晶片的第一面上，（ii）抛光半导体晶片的第一侧以从其中除去物质并露出第一反射物质，该物质包括第二反射物质 物质和中间材料，（iii）检测在引导步骤中引导的光是否同时被（A）位于基底上的第一反射物质反射，以及（B）位于通道中的第二反射物质，并产生端点 检测信号，以及（iv）响应于端点检测信号的产生而终止抛光步骤。 还公开了一种相关装置。

公开(公告)号：US06284586B1

公开(公告)日：2001-09-04

申请号：US09431439

申请日：1999-11-01

Applicant: John J. Seliskar ,  Derryl D. J. Allman ,  John W. Gregory ,  James P. Yakura ,  Dim Lee Kwong

Inventor： John J. Seliskar ,  Derryl D. J. Allman ,  John W. Gregory ,  James P. Yakura ,  Dim Lee Kwong

IPC: H01L27148

CPC classification number: H01L28/40 ,  H01L27/0688 ,  H01L29/42324

Abstract: The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

Abstract translation: 本发明涉及半导体器件，优选电容器及其形成方法。 该方法在制造过程中仅添加一个附加的掩模步骤，并且减少了与各种层的对准有关的问题。 在底部电极上形成相对较厚的绝缘层。 具有使用掩模在绝缘层中蚀刻以暴露底部电极的一部分的侧壁的开口。 一旦去除了掩模，然后在包括侧壁的整个结构上依次沉积介电层和导电层。 此后，使用化学机械抛光来去除导电层和电介质层的部分，使得保留的导电层和电介质层形成例如集成电路电容器的顶部电极和电介质层。 因此，顶部电极设置在保留电介质层的中心区域之间以及保留在电介质层的外围区域之间。

公开(公告)号：US5523964A

公开(公告)日：1996-06-04

申请号：US224241

申请日：1994-04-07

Applicant: Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

Inventor： Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

IPC: G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/22 ,  G11C11/223

Abstract: An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf

Abstract translation: 集成电路非易失性非破坏性读出存储单元包括具有第一和第二电极的铁电电容器，电容Cf和区域Af，以及具有形成栅极电容器的栅极，源极和漏极的晶体管 具有面积Ag和栅极电容Cg，栅极重叠b和沟道深度a，其中电容器第一电极连接到晶体管的栅极。 铁电材料具有介电常数εf，栅极绝缘体具有介电常数εg。 恒定参考电压的源可连接到第一电极。 位线连接到第二电极。 在一个实施例中，第一电极和栅极是相同的导电构件。 在另一个实施例中，第二电极和栅极是相同的导电构件，并且第一电极由晶体管源的延伸和栅极下方的漏极形成，铁电材料在源极和漏极延伸部分之间以及栅极之间。 存储器单元具有参数关系：Cf <5xCg，Af / = 2a和epsilon g> / = epsilon f / 8。

公开(公告)号：US06528389B1

公开(公告)日：2003-03-04

申请号：US09213948

申请日：1998-12-17

Applicant: Derryl D. J. Allman ,  John W. Gregory

Inventor： Derryl D. J. Allman ,  John W. Gregory

IPC: H01L2146

CPC classification number: H01L21/31053 ,  H01L21/76224

Abstract: This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material. In addition a polysilicon stop layer may be exposed to a thermal cycle and oxidized into silicon dioxide after some degree of planarization to further regulate chemical mechanical polishing.

Abstract translation: 本发明包括一种改进的平面化方法，形成在半导体衬底和平坦化半导体衬底上的集成电路。 通过使用由填充层分离的第一和第二停止层来实现改进的平面性。 第一停止层用于限定有源和沟槽区域。 然后将填料层施加在衬底的表面上，并且在填充层的顶部上施加第二阻挡层。 第二停止层通过蚀刻图案化。 蚀刻到第二停止层中的图案用于控制使表面平坦化的化学机械抛光。 模式可以是活动掩码或连续模式的反向图像。 此外，CMP可以用于在施加第二停止层之前创建平衡平面状态。 停止层可以包括多晶硅，氮化硅或比用作填充材料的电介质氧化物材料更硬的另一种材料。 此外，多晶硅停止层可以暴露于热循环，并在一定程度的平坦化之后被氧化成二氧化硅，以进一步调节化学机械抛光。

公开(公告)号：US06168502A

公开(公告)日：2001-01-02

申请号：US09211024

申请日：1998-12-14

Applicant: Derryl D. J. Allman ,  John W. Gregory

Inventor： Derryl D. J. Allman ,  John W. Gregory

IPC: B24B100

CPC classification number: B24B53/017 ,  B24B1/04 ,  Y10S451/91

Abstract: The present invention provides a method and apparatus for conditioning a polishing pad in which slurry is directed under pressure at the polishing pad. Additionally, energy (i.e., ultrasonic energy) may be added to the slurry as it is directed towards the polishing pad, wherein embedded material in the polishing pad is removed or dislodged.

Abstract translation: 本发明提供了一种用于调节抛光垫的方法和装置，其中浆料在抛光垫处被压力地定向。 此外，能量（即，超声能量）可以被引入抛光垫而被添加到浆料中，其中抛光垫中的嵌入材料被去除或移动。

公开(公告)号：US6121147A

公开(公告)日：2000-09-19

申请号：US209704

申请日：1998-12-11

Applicant: David W. Daniel ,  John W. Gregory ,  Derryl D. J. Allman

Inventor： David W. Daniel ,  John W. Gregory ,  Derryl D. J. Allman

IPC: B24B37/04 ,  B24B49/12 ,  B24B57/02 ,  H01L21/3105 ,  H01L21/00

CPC classification number: B24B37/04 ,  B24B49/12 ,  B24B57/02 ,  H01L21/31053

Abstract: A method of planarizing a semiconductor wafer to a distance from a semiconductor substrate of the wafer is disclosed. The method includes the step of forming in the wafer a metallic reporting substance that is at the predetermined distance from the substrate of the wafer. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method further includes the step of utilizing an atomic absorption spectroscopic technique to detect the presence of the metallic reporting substance in the material removed from the wafer. Moreover, the method includes the step of terminating the polishing step in response to the detection of the metallic reporting substance. An associated apparatus for polishing a semiconductor wafer down to a metallic reporting substance of the wafer is also described.

Abstract translation: 公开了一种将半导体晶片平面化到与晶片的半导体衬底一段距离的方法。 该方法包括在晶片上形成距晶片基板预定距离的金属报告物质的步骤。 该方法还包括抛光晶片的第一侧以从晶片去除材料的步骤。 该方法还包括利用原子吸收光谱技术来检测从晶片去除的材料中金属报告物质的存在的步骤。 此外，该方法包括响应于金属报告物质的检测终止抛光步骤的步骤。 还描述了用于将半导体晶片抛光到晶片的金属报告物质的相关设备。

公开(公告)号：US06541383B1

公开(公告)日：2003-04-01

申请号：US09607169

申请日：2000-06-29

Applicant: Derryl D. J. Allman ,  John W. Gregory

Inventor： Derryl D. J. Allman ,  John W. Gregory

IPC: H01L21302

CPC classification number: B24B53/017 ,  B24B37/042 ,  H01L21/31053 ,  H01L21/3212

Abstract: An arrangement for planarizing a surface of a semiconductor wafer. The arrangement includes a planarizing member having a planarizing surface configured to be (i) positioned in contact with and (ii) moved relative to the surface of the semiconductor wafer so as to remove material from the surface of the semiconductor wafer such that the surface of the semiconductor wafer is planarized. The arrangement also includes an adherence promoting ligand chemically bonded to the planarizing surface of the planarizing member. The arrangement further includes an abrasion particle chemically bonded to the adherence promoting ligand such that the abrasion particle is attached to the planarizing surface of the planarizing member. The arrangement also includes a conditioning bar having a conditioning portion positioned in contact with a wafer track defined on the planarizing member. The conditioning portion is configured so that the conditioning portion extends completely across the wafer track. The arrangement still further includes a wafer carrier which (i) urges the surface of the semiconductor wafer against the planarizing surface at a first pressure for a first period of time and (ii) urges the surface of the semiconductor wafer against the planarizing surface at a second pressure for a second period of time. The first pressure is greater than the second pressure such that slurry is advanced from an outer periphery of the semiconductor wafer toward a center portion of the semiconductor wafer. An associated method of planarizing a surface of a semiconductor wafer is also disclosed.

Abstract translation: 用于平坦化半导体晶片的表面的布置。 该布置包括具有平坦化表面的平坦化构件，该平坦化构件被配置成（i）定位成与半导体晶片的表面接触和（ii）移动，以便从半导体晶片的表面去除材料， 半导体晶片被平坦化。 该布置还包括与平坦化构件的平坦化表面化学键合的粘附促进配体。 该布置还包括与粘附促进配体化学结合的磨损颗粒，使得磨损颗粒附着到平坦化构件的平坦化表面。 该布置还包括调节杆，其具有定位成与平坦化构件上限定的晶片轨道接触的调节部分。 调理部分被配置成使得调理部分完全延伸穿过晶片轨道。 该装置还包括晶片载体，其（i）在第一时间段内以第一压力将半导体晶片的表面压在平坦化表面上，并且（ii）在半导体晶片的表面上以一个 第二次压力第二次。 第一压力大于第二压力，使得浆料从半导体晶片的外周朝向半导体晶片的中心部分前进。 还公开了一种使半导体晶片的表面平坦化的相关方法。