公开(公告)号：US06065113A

公开(公告)日：2000-05-16

申请号：US813887

申请日：1997-03-07

申请人： Jonathan H. Shiell ,  Joel J. Graber ,  Donald E. Steiss

发明人： Jonathan H. Shiell ,  Joel J. Graber ,  Donald E. Steiss

IPC分类号： G06F1/00 ,  G06F9/30 ,  G06F11/00 ,  G06F9/00

CPC分类号： G06F9/3017 ,  G06F11/006 ,  G06F9/30003

摘要： In a method embodiment (10), the method operates a microprocessor (110), and the microprocessor has an instruction set. The method first (11) stores an identifier code uniquely identifying the particular microprocessor in a one-time programmable register. The method second (12) issues to the microprocessor an identifier request instruction from the instruction set. The method then, and in response to the identifier request instruction, provides (18) from the microprocessor an identifier code. Other circuits, systems, and methods are also disclosed and claimed.

摘要翻译： 在方法实施例（10）中，该方法操作微处理器（110），并且微处理器具有指令集。 方法第一（11）将唯一地标识特定微处理器的识别码存储在一次性可编程寄存器中。 方法二（12）向微处理器发出来自指令集的标识符请求指令。 该方法然后响应于标识符请求指令，从微处理器提供（18）标识符代码。 还公开并要求保护其他电路，系统和方法。

公开(公告)号：US5850543A

公开(公告)日：1998-12-15

申请号：US741878

申请日：1996-10-30

申请人： Jonathan H. Shiell ,  Donald E. Steiss

发明人： Jonathan H. Shiell ,  Donald E. Steiss

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3842

摘要： A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer and a return address stack, each having multiple entries. Each entry includes an address value corresponding to the destination of a branching instruction, and an associated register value, such as a stack pointer. Upon the execution of a subroutine call, the return address and current stack pointer value are stored in the return address stack, to allow for fetching and speculative execution of the sequential instructions following the call in the calling program. Any branching instruction, such as the call, return, or conditional branch, will have an entry included in the branch target buffer; upon fetch of the branch on later passes, speculative execution from the target address can begin using the stack pointer value stored speculatively in the branch target buffer in association with the target address.

摘要翻译： 公开了具有推测执行能力的超标量流水线型微处理器。 推测执行在具有分支目标缓冲器和返回地址堆栈的获取单元的控制下，每个具有多个条目。 每个条目包括与分支指令的目的地相对应的地址值和相关联的寄存器值，诸如堆栈指针。 在执行子程序调用时，返回地址和当前堆栈指针值存储在返回地址堆栈中，以允许在调用程序中的调用之后提取和推测执行顺序指令。 任何分支指令（如调用，返回或条件分支）将具有包含在分支目标缓冲区中的条目; 在稍后通过分支提取时，从目标地址的推测执行可以开始使用与目标地址相关联的分支目标缓冲器中的推测性地存储的堆栈指针值。

公开(公告)号：US06442667B1

公开(公告)日：2002-08-27

申请号：US09314557

申请日：1999-05-19

申请人： Jonathan H. Shiell ,  Donald E. Steiss

发明人： Jonathan H. Shiell ,  Donald E. Steiss

IPC分类号： G06F1200

CPC分类号： G06F12/0893 ,  G06F12/1054 ,  G06F2212/1028 ,  Y02D10/13

摘要： This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a first predetermined set of address bits. A second decoder selectively powers one of the X rows corresponding to a second predetermined set of address bits. Multiplexers select the powered memory bank for data access. Thus one of the plural memory banks is powered and selected for memory access corresponding to the first and second predetermined sets of bits of the received address. This memory system is preferably a cache memory including a further column of memory banks for cache addresses and cache control data including at least a cache valid tag. A multiplexer selects one row corresponding to the second predetermined set of address bits. A valid and equal unit indicates whether data received from the third multiplexer includes a cache valid tag indicating a valid address and a cache address matching the received address. This indicates a cache hit.

摘要翻译： 本发明是包括逻辑地设置在X行和Y列的阵列中的多个存储体的存储器系统。 第一解码器选择性地对与第一预定的地址位集合对应的Y列之一供电。 第二解码器选择性地对应于第二预定地址位组的X行中的一个。 多路复用器选择供电的存储器进行数据访问。 因此，为接收地址的第一和第二预定位组对应的存储器访问供电和选择多个存储体之一。 该存储器系统优选地是高速缓存存储器，其包括用于高速缓存地址的另一列存储器组和至少包括高速缓存有效标签的高速缓存控制数据。 多路选择器选择与第二预定地址位组对应的一行。 有效和相等的单位指示从第三多路复用器接收的数据是否包括指示有效地址的高速缓存有效标签和与接收到的地址匹配的高速缓存地址。 这表示缓存命中。

公开(公告)号：US5961632A

公开(公告)日：1999-10-05

申请号：US897998

申请日：1997-07-25

申请人： Jonathan H. Shiell ,  Donald E. Steiss

发明人： Jonathan H. Shiell ,  Donald E. Steiss

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30196 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/3867

摘要： A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.

摘要翻译： 处理器根据所公开的方法处理多个指令。 首先，该方法接收（32）来自多个指令的指令。 第二，该方法确定（34）接收到的指令是否在指令路径引导代码之前。 第三，该方法沿着多条指令路径中的至少一条指令路径通过（36或38）所接收的指令。 第四，响应于确定接收到的指令之前是指令路径引导码，该方法执行与所接收的指令相对应并且从多条指令路径之一中选择的机器字。 具体地，响应于指令路径引导码选择所选择的指令路径。

公开(公告)号：US5913049A

公开(公告)日：1999-06-15

申请号：US903847

申请日：1997-07-31

申请人： Jonathan H. Shiell ,  Donald E. Steiss

发明人： Jonathan H. Shiell ,  Donald E. Steiss

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3812 ,  G06F9/3822 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3861

摘要： A microprocessor (10) and system (2) including a multi-stream pipeline unit (25) are disclosed. The multi-stream pipeline unit (25) includes individual fetch units (26), instruction caches (16.sub.i), and decoders (34) in separate instruction streams (PROC0, PROC1) or pipelines. A common scheduler (36) is provided to check for dependencies among the instructions from the multiple instruction streams (PROC0, PROC1), and to launch instructions for execution by the various execution units (31, 40, 42, 50), including a microcode unit (47). A common register file (39) includes register banks (70) dedicated to each pipeline, and also a register bank (72) that includes temporary and shared registers available to instructions of either instruction stream (PROC0, PROC1), such as useful in the event of register renaming due to a dependency. Each decoded instruction in the scheduler (36) has an identifier (PROC) indicating the one of the instruction streams (PROC0, PROC1) from which it was issued. In the event of an exception requiring one of the pipelines to be flushed, the decoded instructions in the scheduler (36) associated with the flushed pipeline may be invalidated (i.e., the results of their execution ignored), while the instructions in the scheduler (36) associated with the other pipeline may continue to advance and execute normally.

摘要翻译： 公开了一种包括多流管线单元（25）的微处理器（10）和系统（2）。 多流流水线单元（25）包括单独的指令流（PROC0，PROC1）或管线中的各个取指单元（26），指令高速缓存（16i）和解码器（34）。 公共调度器（36）被提供用于检查来自多个指令流（PROC0，PROC1）的指令之间的相关性，并且启动由各种执行单元（31,40,42,50）执行的指令，包括微代码 单位（47）。 公共寄存器文件（39）包括专用于每个流水线的寄存器组（70），还包括寄存器组（72），其包括可用于任一指令流（PROC0，PROC1）的指令的临时和共享寄存器， 由于依赖关系，注册重命名事件。 调度器（36）中的每个解码指令都具有指示从其发出的指令流（PROC0，PROC1）之一的标识符（PROC）。 在需要冲洗流水线的异常的情况下，与冲洗流水线相关联的调度器（36）中的解码指令可以被无效（即，其忽略的执行结果），而调度器 36）可以继续前进并且正常地执行。

公开(公告)号：US5903742A

公开(公告)日：1999-05-11

申请号：US739594

申请日：1996-10-30

申请人： Jonathan H. Shiell ,  Donald E. Steiss

发明人： Jonathan H. Shiell ,  Donald E. Steiss

IPC分类号： G06F9/32 ,  G06F9/445 ,  G06F3/00 ,  G06F9/00 ,  G06F3/42

CPC分类号： G06F9/30094 ,  G06F9/4403

摘要： A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predetermined bit has the first state. Each additional bit is not writable when the predetermined bit has the second state. The microprocessor further includes at least one circuit controlled by the state of a corresponding one of the additional bits of the control register. The writability of the additional bits is preferably further conditioned upon the state of a machine status register, which is unconditionally writable to either the first state or the second state. A primary AND gate and a secondary AND gate corresponding to each additional bit control the writability of the additional bits. The secondary AND gates may further condition the writability of the corresponding additional bit on the state of a secondary machine status register, the current privilege level or other microprocessor status signals or plural additional inputs. Each bit of the control register is written into a corresponding bit of the shadow register upon writing the second state into the machine status register.

摘要翻译： 微处理器包括控制寄存器，该控制寄存器具有无条件地可写入第一状态或第二状态的预定位。 当预定位具有第一状态时，控制寄存器的附加位可写入第一或第二状态。 当预定位具有第二状态时，每个附加位不可写。 微处理器还包括由控制寄存器的相应一个附加位的状态控制的至少一个电路。 优选地，附加比特的可写性进一步受机器状态寄存器的状态的限制，该状态寄存器无级可写到第一状态或第二状态。 对应于每个附加位的主与门和辅助AND门控制附加位的可写性。 辅AND门可以进一步调节辅助机器状态寄存器状态，当前权限级别或其他微处理器状态信号或多个附加输入的相应附加位的可写性。 将第二个状态写入机器状态寄存器时，将控制寄存器的每一位写入影子寄存器的相应位。

公开(公告)号：US06449692B1

公开(公告)日：2002-09-10

申请号：US09212034

申请日：1998-12-15

申请人： Steven D. Krueger ,  Jonathan H. Shiell ,  Ian Chen

发明人： Steven D. Krueger ,  Jonathan H. Shiell ,  Ian Chen

IPC分类号： G06F1208

CPC分类号： G06F12/0897 ,  G06F3/14 ,  G06F12/0848 ,  G06F12/0875 ,  G09G2360/121

摘要： A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

摘要翻译： 一种包括中央处理单元（12）和存储器层级的计算机系统（8）。 存储器层级包括第一高速缓存存储器（16）和第二高速缓存存储器（26）。 第一高速缓冲存储器可操作以存储非像素信息，其中非像素信息可被中央处理单元处理。 第二高速缓冲存储器在存储器层级中高于第一高速缓冲存储器，并且具有可操作用于存储非像素信息（26b）和像素数据（26a）的多个存储位置。 最后，计算机系统包括高速缓存控制电路（24），用于动态分配存储位置的数量，使得第一组存储位置用于存储非像素信息，并且第二组存储位置用于存储像素 数据。

公开(公告)号：US6065125A

公开(公告)日：2000-05-16

申请号：US741876

申请日：1996-10-30

申请人： Jonathan H. Shiell ,  Ian Chen

发明人： Jonathan H. Shiell ,  Ian Chen

IPC分类号： G06F1/32 ,  G06F13/14

CPC分类号： G06F1/3203

摘要： Circuits, systems, and methods relating to operating a computer system operable in a system manager mode (24). The method includes various steps. The first step (34) occurs during operation of the computer system (10) at a time other than start-up, and receives user power management data from a user of the computer system. The second step (38) stores the user power management data in memory space (30) accessible by the system management mode. The third step (40) accesses the user power management data from the memory space. Finally, the fourth step (42) controls at least one peripheral (14, 16, 18, 20) of the computer system in response to the accessed user power management data.

摘要翻译： 与操作以系统管理器模式操作的计算机系统相关的电路，系统和方法（24）。 该方法包括各种步骤。 第一步骤（34）在计算机系统（10）的操作期间发生在除了启动之外的时间，并且从计算机系统的用户接收用户电力管理数据。 第二步骤（38）将用户电源管理数据存储在可由系统管理模式访问的存储器空间（30）中。 第三步（40）从存储器空间访问用户电源管理数据。 最后，第四步骤（42）响应于所访问的用户电源管理数据来控制计算机系统的至少一个外围设备（14,16,18,20）。

公开(公告)号：US06401212B1

公开(公告)日：2002-06-04

申请号：US09708299

申请日：2000-11-08

申请人： James O. Bondi ,  Jonathan H. Shiell

发明人： James O. Bondi ,  Jonathan H. Shiell

IPC分类号： G06F132

CPC分类号： G06F12/0862 ,  G06F9/3824

摘要： In a computer system (10) embodiment, there is included a memory (18) and circuitry (16a) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (14), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (16b, 16n, 17) using the system resource. The system further includes circuitry (20, 22, 24) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (26) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.

摘要翻译： 在计算机系统（10）实施例中，包括用于响应于预取请求从存储器预取信息的存储器（18）和电路（16a）。 系统还包括系统资源（14），其中系统资源响应于用于预取信息的电路的预取操作而负担。 响应于使用系统资源的其它电路（16b，16n，17），系统资源也进一步负担。 该系统还包括用于确定系统资源负担的度量的电路（20,22,24）。 最后，该系统包括电路（26），用于响应于负担测量与阈值的比较，禁止通过电路预取信息以预取信息。 还公开并要求保护其他电路，系统和方法。

公开(公告)号：US06338137B1

公开(公告)日：2002-01-08

申请号：US09314763

申请日：1999-05-19

申请人： Jonathan H. Shiell ,  Patrick W. Bosshart

发明人： Jonathan H. Shiell ,  Patrick W. Bosshart

IPC分类号： G06F9312

CPC分类号： G06F9/325 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3873

摘要： A multiple cycle memory access unit issues a memory access load or store, delaying a predetermined number of instruction cycles between it activation and its initial data transfer. The multiple cycle memory access unit controls a predetermined plural number of accesses and operates independently and in parallel with the instruction flow of the data processor. The multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers. This predetermined period may be the same as the initial delay or it may be determined independent of the initial delay. The operation of the multiple cycle memory access unit is subject to predication on an instruction specified data registers. The multiple cycle memory access unit preferably provides predetermined register number cycling among the plural data registers. The multiple cycle memory access unit preferably aborts operation, stops and saves its internal state on a predetermined event.

摘要翻译： 多周期存储器访问单元发出存储器访问负载或存储，延迟其激活和其初始数据传输之间的预定数量的指令周期。 多周期存储器访问单元控制预定的多个访问，并且与数据处理器的指令流独立地并行操作。 多周期存储器访问单元在预定数量的数据传输的顺序数据传送之间延迟预定数量的指令周期。 该预定周期可以与初始延迟相同，或者可以独立于初始延迟来确定。 多周期存储器访问单元的操作可以对指令指定的数据寄存器进行预测。 多周期存储器访问单元优选地在多个数据寄存器之间提供预定的寄存器数循环。 多周期存储器访问单元优选地中止操作，停止并将其内部状态保存在预定事件上。