公开(公告)号：US5441904A

公开(公告)日：1995-08-15

申请号：US341892

申请日：1994-11-15

申请人： Jong C. Kim ,  Sang H. Woo

发明人： Jong C. Kim ,  Sang H. Woo

IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L21/28061

摘要： A method is disclosed for forming a gate electrode having two polysilicon layers and a tungsten silicide layer to prevent fluorine gas diffusion along grain boundaries from penetrating into a gate oxide film.This method for forming a gate electrode is comprised of sequentially forming a gate oxide film and a first polysilicon layer on a silicon substrate, enlarging the grain size of the first polysilicon layer by heat treatment, introducing a reagent gas, either SiH.sub.4 or Si.sub.2 H.sub.6, to further adjust the grain size within said layer, forming a second polysilicon layer on the first polysilicon layer, enlarging the grain size of the second polysilicon layer by heat treatment, introducing a reagent gas, either Si.sub.2 H.sub.6 or SiH.sub.4, whichever one was not used to treat the first polysilicon layer, forming a tungsten silicide layer on the second polysilicon layer, and patterning the tungsten silicide layer, the second polysilicon layer and the first polysilicon layer by means of a mask etching process.

摘要翻译： 公开了一种形成具有两个多晶硅层和硅化钨层的栅电极的方法，以防止沿着晶界的氟气扩散渗透到栅极氧化膜中。 这种形成栅电极的方法包括在硅衬底上依次形成栅极氧化膜和第一多晶硅层，通过热处理扩大第一多晶硅层的晶粒尺寸，将SiH4或Si2H6的反应气引入到 进一步调整所述层内的晶粒尺寸，在第一多晶硅层上形成第二多晶硅层，通过热处理扩大第二多晶硅层的晶粒尺寸，引入Si2H6或SiH4的反应气体，无论哪一种都不用于处理 第一多晶硅层，在第二多晶硅层上形成硅化钨层，并通过掩模蚀刻工艺对硅化钨层，第二多晶硅层和第一多晶硅层进行构图。

公开(公告)号：US5405799A

公开(公告)日：1995-04-11

申请号：US138204

申请日：1993-10-20

申请人： Sang H. Woo ,  Ha E. Jeon ,  Young J. Park

发明人： Sang H. Woo ,  Ha E. Jeon ,  Young J. Park

IPC分类号： H01L21/28 ,  H01L21/033 ,  H01L21/306 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L21/0337 ,  H01L27/10817

摘要： A storage electrode of a DRAM cell in a highly-integrated semiconductor device has, in order to secure the surface area thereof greater than that of a conventional tunnel-type storage electrode, an upper plate of storage electrode formed over a lower plate of storage electrode separated therefrom by a predetermined distance, while interposing bars of various shapes formed of a conductive layer to electrically connect the upper and lower plates, and a method for manufacturing the storage electrode is also provided.

摘要翻译： 高集成度半导体装置中的DRAM单元的存储电极为了确保其表面积比常规的隧道式存储电极的表面积更大，存储电极的上板形成在存储电极的下板上 与预定距离分离，同时插入由导电层形成的各种形状的条以电连接上板和下板，还提供了用于制造存储电极的方法。

公开(公告)号：US5429961A

公开(公告)日：1995-07-04

申请号：US127968

申请日：1993-09-28

申请人： Sang H. Woo ,  Ha E. Jeon

发明人： Sang H. Woo ,  Ha E. Jeon

IPC分类号： H01L21/335 ,  H01L21/20 ,  H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/86

CPC分类号： H01L21/2022 ,  H01L27/1108 ,  Y10S148/003 ,  Y10S148/122

摘要： A method for manufacturing a TFT of a SRAM in a highly-integrated semiconductor device, to enlarge the grain size of a polysilicon film, includes steps of depositing amorphous silicon film under a pressure capable of maintaining a uniform thickness thereof, and forming a polysilicon film which has a maximized grain size in the same tube that the amorphous silicon film has been deposited, while performing an annealing process by raising the temperature to 600.degree.-650.degree. C. for 4-10 hours under the pressure which is lowered to approximately 10.sup.-3 Torr. The polysilicon film having a maximized grain size is utilized as the channels of the TFT.

摘要翻译： 一种用于制造高集成度半导体器件中的SRAM的TFT以扩大多晶硅膜的晶粒尺寸的方法包括以下步骤：在能够保持其厚度均匀的压力下沉积非晶硅膜，并形成多晶硅膜 其在与非晶硅膜沉积的同一管中具有最大的晶粒尺寸，同时通过将温度升高至600-650℃进行退火处理4-10小时，压力降至约10 -3乇 具有最大晶粒尺寸的多晶硅膜被用作TFT的沟道。

公开(公告)号：US5561310A

公开(公告)日：1996-10-01

申请号：US380654

申请日：1995-01-30

申请人： Sang H. Woo ,  Ha E. Jeon ,  Young J. Park

发明人： Sang H. Woo ,  Ha E. Jeon ,  Young J. Park

IPC分类号： H01L21/28 ,  H01L21/033 ,  H01L21/306 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/0337 ,  H01L27/10817

摘要： A storage electrode of a DRAM cell in a highly-integrated semiconductor device has, in order to secure the surface area thereof greater than that of a conventional tunnel-type storage electrode, an upper plate of storage electrode formed over a lower plate of storage electrode separated therefrom by a predetermined distance, while interposing bars of irregularly shapes formed of a conductive layer to electrically connect the upper and lower plates.

摘要翻译： 高集成度半导体装置中的DRAM单元的存储电极为了确保其表面积比常规的隧道式存储电极的表面积更大，存储电极的上板形成在存储电极的下板上 与其隔开预定距离，同时插入由导电层形成的不规则形状的条以电连接上板和下板。

公开(公告)号：US5532182A

公开(公告)日：1996-07-02

申请号：US365562

申请日：1994-12-28

申请人： Sang H. Woo

发明人： Sang H. Woo

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87

摘要： There is disclosed a method for the fabrication of a capacitor of a DRAM, comprising the characteristic steps of: forming a bellows type storage electrode; depositing an impurity-doped polysilicon film on the entire surface of the storage electrode; and diffusing the dopants into impurity-rare edge portions of the storage electrode through an annealing treatment. Accordingly, it is capable of easily securing the capacitance of a capacitor in greater quantity per unit area, and thus, effects a reduction in production cost.

摘要翻译： 公开了一种用于制造DRAM的电容器的方法，包括以下特征性步骤：形成波纹管式存储电极; 在所述存储电极的整个表面上沉积杂质掺杂多晶硅膜; 并通过退火处理将掺杂剂扩散到存储电极的杂质稀有边缘部分。 因此，能够容易地确保每单位面积的电容器的电容量，从而降低生产成本。

公开(公告)号：US08962261B2

公开(公告)日：2015-02-24

申请号：US14001827

申请日：2012-04-06

申请人： Minnie M. Sarwal ,  Tara Sigdel ,  Sang H. Woo ,  Richard Lafayette

发明人： Minnie M. Sarwal ,  Tara Sigdel ,  Sang H. Woo ,  Richard Lafayette

IPC分类号： G01N33/53 ,  G01N33/68 ,  G01N33/564

CPC分类号： G01N33/6854 ,  G01N33/564 ,  G01N33/6893 ,  G01N2800/347

摘要： Aspects of the present invention include methods for diagnosing and monitoring IgAN in a subject. In practicing one aspect of the subject methods, a sample from a subject is analyzed for the presence of one or more specific autoantibodies to determine the IgAN phenotype of the subject. Also provided are compositions, systems, kits and computer program products that find use in practicing the subject methods. The methods and compositions find use in a variety of applications.

摘要翻译： 本发明的方面包括用于诊断和监测受试者中IgAN的方法。 在实施本发明方法的一个方面时，分析来自受试者的样品中存在一种或多种特异性自身抗体以确定受试者的IgAN表型。 还提供了用于实践主题方法的组合物，系统，试剂盒和计算机程序产品。 这些方法和组合物可用于各种应用。

公开(公告)号：US20140141449A1

公开(公告)日：2014-05-22

申请号：US14001827

申请日：2012-04-06

申请人： Minnie M. Sarwal ,  Tara Sigdel ,  Sang H. Woo ,  Richard Lafayette

发明人： Minnie M. Sarwal ,  Tara Sigdel ,  Sang H. Woo ,  Richard Lafayette

IPC分类号： G01N33/68

CPC分类号： G01N33/6854 ,  G01N33/564 ,  G01N33/6893 ,  G01N2800/347

摘要： Aspects of the present invention include methods for diagnosing and monitoring IgAN in a subject. In practicing one aspect of the subject methods, a sample from a subject is analyzed for the presence of one or more specific autoantibodies to determine the IgAN phenotype of the subject. Also provided are compositions, systems, kits and computer program products that find use in practicing the subject methods. The methods and compositions find use in a variety of applications.

摘要翻译： 本发明的方面包括用于诊断和监测受试者中IgAN的方法。 在实施本发明方法的一个方面时，分析来自受试者的样品中存在一种或多种特异性自身抗体以确定受试者的IgAN表型。 还提供了用于实践主题方法的组合物，系统，试剂盒和计算机程序产品。 这些方法和组合物可用于各种应用。

公开(公告)号：US5518966A

公开(公告)日：1996-05-21

申请号：US363358

申请日：1994-12-23

申请人： Sang H. Woo

发明人： Sang H. Woo

IPC分类号： H01L21/3213 ,  H01L21/469

CPC分类号： H01L21/32134 ,  Y10S438/924

摘要： A method is disclosed for the wet etching of polysilicon, which comprises the steps of: annealing a lamination structure of a doped polysilicon and an undoped polysilicon at a predetermined temperature for a predetermined period; and applying to the annealed lamination structure a chemical etchant comprising nitric acid, fluoric acid, acetic acid and deionized water with the volume ratio of nitric acid to acetic acid to fluoric acid to deionized water being 30:3:x:15+(1-x) wherein x is a real number ranging from 0.2 to 1.0, so as to remove the doped polysilicon film. Instead of fluoric acid, alcohol may be used in the chemical etchant without affecting the etching selectivity. This method is superior in performance with regard to selective etching between the undoped polysilicon and the doped polysilicon. Therefore, the doped polysilicon which is useful in many ways, for example, storage electrode, insertion layer and contact, can be etched in such a thickness as is needed, with the chemical etchant. Consequently, the present method is very useful in developing new semiconductor devices.

摘要翻译： 公开了一种用于多晶硅的湿蚀刻的方法，其包括以下步骤：在预定温度下将掺杂多晶硅和未掺杂多晶硅的叠层结构退火预定时间; 并且向退火的层压结构施加包含硝酸，氟酸，乙酸和去离子水的化学蚀刻剂，其硝酸与乙酸与氟酸与去离子水的体积比为30:3:x:15+（1- x）其中x是从0.2到1.0的实数，以便去除掺杂的多晶硅膜。 代替氟酸，可以在化学蚀刻剂中使用醇，而不影响蚀刻选择性。 该方法在未掺杂多晶硅和掺杂多晶硅之间的选择性蚀刻方面性能优异。 因此，可以以许多方式使用的掺杂多晶硅，例如存储电极，插入层和接触，可以用化学蚀刻剂所需的厚度进行蚀刻。 因此，本发明的方法在开发新的半导体器件方面是非常有用的。

公开(公告)号：US5476805A

公开(公告)日：1995-12-19

申请号：US151182

申请日：1993-11-12

申请人： Sang H. Woo ,  Ha E. Jeon

发明人： Sang H. Woo ,  Ha E. Jeon

IPC分类号： H01L21/28 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852

摘要： A method for fabricating a storage electrode of a DRAM cell capable of preventing impurities from excessively moving from the storage electrode to diffusion regions. The storage electrode is formed by a double formation of polysilicon layers. An undoped polysilicon layer 11 is primarily deposited over the entire exposed surface of the resulting structure to a thickness corresponding to 40 to 50% of a predetermined thickness of the storage electrode. A doped polysilicon layer is secondarily deposited over the undoped polysilicon layer to a thickness corresponding to 60 to 50% of the predetermined thickness of the storage electrode. The doped polysilicon layer and the undoped polysilicon layer are subjected to a patterning so that predetermined portions thereof are removed so as to form the storage electrode.

摘要翻译： 一种用于制造能够防止杂质从存储电极过度移动到扩散区域的DRAM单元的存储电极的方法。 存储电极通过双重形成多晶硅层形成。 未掺杂的多晶硅层11主要沉积在所得结构的整个暴露表面上，其厚度对应于存储电极的预定厚度的40至50％。 掺杂多晶硅层二次沉积在未掺杂的多晶硅层上，其厚度对应于存储电极的预定厚度的60％至50％。 对掺杂多晶硅层和未掺杂的多晶硅层进行图案化，以使其预定部分被去除以形成存储电极。