公开(公告)号：US06772359B2

公开(公告)日：2004-08-03

申请号：US09725896

申请日：2000-11-30

申请人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

发明人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

IPC分类号： G06F104

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G11C7/22 ,  G11C11/4076 ,  Y02D10/13 ,  Y02D10/14

摘要： A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command. Our circuit includes: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with a device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with a device address value of a COLX packet is enabled, and when the command is a read or current control command; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting a control signal for maintaining the clock enable signal to the signal generating unit in the read or current control command; and an output signal control unit for outputting a control signal for controlling generation of the clock enable signal to the signal generating unit, when the command is not the read or current control command.

摘要翻译： 提供了一种用于Rambus DRAM的时钟控制电路，其通过预先确定所应用的命令是读取还是当前控制命令来降低功耗，并且仅在读取或当前控制命令期间启用用于外部输出内部数据的时钟信号。 我们的电路包括：输入信号检测单元，用于当将所选择的Rambus DRAM的地址值与COLC分组的设备地址值进行比较的第一比较信号中的一个产生使能信号，以及第二比较信号， 所选择的具有COLX分组的设备地址值的Rambus DRAM被使能，并且当命令是读取或当前控制命令时; 信号产生单元，用于当所述第一和第二比较信号之一被使能时，产生用于外部输出内部数据的时钟使能信号; 输出信号维持单元，用于在读取或当前控制命令中输出用于将时钟使能信号保持到信号生成单元的控制信号; 以及输出信号控制单元，用于当命令不是读取或当前控制命令时，向信号生成单元输出用于控制产生时钟使能信号的控制信号。

公开(公告)号：US06687843B2

公开(公告)日：2004-02-03

申请号：US09725899

申请日：2000-11-30

申请人： Jong Tae Kwak

发明人： Jong Tae Kwak

IPC分类号： G06F104

CPC分类号： G11C7/1072

摘要： The present invention discloses a Rambus DRAM which can reduce power consumption by restricting generation of an unnecessary clock by improving command decryption when a command is applied with a COLC packet or COLX packet, so that the other packet cannot influence on another device.

摘要翻译： 本发明公开了一种Rambus DRAM，其可以通过在用COLC分组或COLX分组应用命令时改进命令解密来限制生成不必要的时钟来降低功耗，使得另一个分组不会影响另一个设备。

公开(公告)号：US06646939B2

公开(公告)日：2003-11-11

申请号：US10206702

申请日：2002-07-26

申请人： Jong Tae Kwak

发明人： Jong Tae Kwak

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C7/1078 ,  G11C7/22 ,  G11C2207/107 ,  G11C2207/2227

摘要： Disclosed is low power type Rambus DRAM including top/bottom memory bank units respectively comprising a plurality of banks for storing data, top and bottom serial/parallel shifter units, an interface logic circuit unit, a delay lock loop (DLL) unit and an input/output block unit. The top serial/parallel shifter unit is connected between the top memory bank unit and the input/output block unit and the bottom serial/parallel shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal outputted from the interface logic circuit unit. The input/output block unit generates a signal for selectively controlling the operation of top and bottom serial/parallel shifter units by buffering the clock signal generated from the DLL unit.

摘要翻译： 公开了低功率型Rambus DRAM，其包括分别包括用于存储数据的多个存储体的顶部/底部存储体单元，顶部和底部串行/并行移位器单元，接口逻辑电路单元，延迟锁定环（DLL）单元和输入 /输出块单元。 顶部串行/并行移位器单元连接在顶部存储体单元和输入/输出块单元之间，底部串行/并行移位器单元连接在底部存储体单元和输入/输出块单元之间。 接口逻辑电路单元根据从外部接收到的读取或写入命令生成用于选择顶部或底部存储体单元的信号。 DLL单元根据从接口逻辑电路单元输出的信号产生时钟信号。 输入/输出块单元通过缓冲从DLL单元产生的时钟信号产生用于选择性地控制顶部和底部串行/并行移位器单元的操作的信号。

公开(公告)号：US06775201B2

公开(公告)日：2004-08-10

申请号：US10299267

申请日：2002-11-19

申请人： Seong Hoon Lee ,  Jong Tae Kwak

发明人： Seong Hoon Lee ,  Jong Tae Kwak

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1012 ,  G11C7/1018 ,  G11C7/1042 ,  G11C7/1051 ,  G11C8/18

摘要： An apparatus for outputting burst read data is disclosed which divides input data into an odd number data group and an even number data group, selects a data group including a bit to be first outputted and synchronizes the data group including the bit at rising edges of a clock signal and a data group not including the bit at falling edges of a clock signal, thereby continuously outputting burst read data at a high speed according to output mode set in mode register set using sequential or interleave modes.

摘要翻译： 公开了一种用于输出脉冲串读取数据的装置，其将输入数据分成奇数数据组和偶数数据组，选择包括要首先输出的位的数据组，并使包括位在第一位的位的数据组同步 时钟信号和在时钟信号的下降沿不包括位的数据组，从而根据使用顺序或交织模式设置在模式寄存器中的输出模式，高速连续输出脉冲串读取数据。

公开(公告)号：US06573771B2

公开(公告)日：2003-06-03

申请号：US10136304

申请日：2002-05-02

申请人： Seong-Hoon Lee ,  Jong Tae Kwak ,  Chang-Ki Kwon

发明人： Seong-Hoon Lee ,  Jong Tae Kwak ,  Chang-Ki Kwon

IPC分类号： H03L706

CPC分类号： H03L7/089 ,  H03L7/0814

摘要： A clock synchronization circuit. The clock synchronization circuit composed of a digital DLL outputs a clock signal delayed by a variable delay line and a clock signal delayed by an additional delay cell, mixes the two clock signals, and outputs an internal clock signal having a smaller delay than a delay time of a delay cell, thereby rapidly precisely synchronizing an external clock signal and the internal clock signal. In addition, a driving unit and a control unit for adjusting a duty cycle are provided to set up a ratio of 50%, thereby improving operation performance.

摘要翻译： 时钟同步电路。 由数字DLL组成的时钟同步电路输出延迟了可变延迟线的时钟信号和延迟了附加延迟单元的时钟信号，混合两个时钟信号，并输出延迟时间比延迟时间小的内部时钟信号 延迟单元，从而快速精确地同步外部时钟信号和内部时钟信号。 此外，提供用于调整占空比的驱动单元和控制单元以设定50％的比率，从而提高操作性能。

公开(公告)号：US06246636B1

公开(公告)日：2001-06-12

申请号：US09604476

申请日：2000-06-27

申请人： Kwang Jin Na ,  Jong Tae Kwak

发明人： Kwang Jin Na ,  Jong Tae Kwak

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

摘要： The present invention relates to a load signal generating circuit of a packet command driving type memory device, in a packet command driving type memory device for generating a load signal for loading data from a core block, a load signal generating circuit of a packet command driving type memory device of the present invention comprises a first signal generating means for receiving a first input signal and generating a first internal signal; a second signal generating means for receiving a second input signal and generating a second internal signal in response to a clock signal; a third signal generating means for receiving a third input signal and generating a third internal signal; a fourth signal generating means for receiving the first internal signal generated from the first signal generating means the second internal signal generated from the second signal generating means as two inputs, selecting and outputting the first internal signal according to the third input signal generated from the third signal generating means or selecting the second internal signal and generating a load signal synchronized to a clock signal.

摘要翻译： 本发明涉及一种分组命令驱动型存储装置的负载信号发生电路，用于产生用于从核心块加载数据的负载信号的分组命令驱动型存储装置，分组命令驱动的负载信号产生电路 本发明的存储装置包括：第一信号发生装置，用于接收第一输入信号并产生第一内部信号; 第二信号发生装置，用于响应于时钟信号接收第二输入信号和产生第二内部信号; 第三信号发生装置，用于接收第三输入信号并产生第三内部信号; 第四信号发生装置，用于接收从第一信号发生装置产生的第一内部信号，从第二信号发生装置产生的第二内部信号作为两个输入，根据从第三信号产生装置产生的第三输入信号选择和输出第一内部信号 信号发生装置或选择第二内部信号并产生与时钟信号同步的负载信号。

公开(公告)号：US07046061B2

公开(公告)日：2006-05-16

申请号：US10978623

申请日：2004-11-01

申请人： Jong Tae Kwak

发明人： Jong Tae Kwak

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0802 ,  H03L7/089

摘要： Disclosed are a delay locked loop (DLL) and a method of driving the same. The delay locked loop includes a clock buffer for buffering an inputted external clock to generate an internal clock, the clock buffer generating a control signal for disabling the internal clock depending on whether the power is down, a delayed line for delaying the internal clock, a clock driver for buffering the output of the delayed line to generate a clock signal, the clock driver disabling the clock signal depending on whether the power is down, a delay monitor for delaying the external clock, a phase detector for detecting the difference in a phase between the internal clock and the output of the delayed monitor to generate a detected signal, the phase detector being disabled according to the control signal, and a shift register for controlling the delayed line according to the detected signal from the phase detector. Therefore, it is possible to sufficiently satisfy power down excitation time while reducing current consumption of the entire semiconductor device during the power down state.

摘要翻译： 公开了一种延迟锁定环（DLL）及其驱动方法。 所述延迟锁定环包括用于缓冲输入的外部时钟以产生内部时钟的时钟缓冲器，所述时钟缓冲器根据所述电源是否断电产生用于禁止所述内部时钟的控制信号，用于延迟所述内部时钟的延迟线， 时钟驱动器，用于缓冲延迟线的输出以产生时钟信号，时钟驱动器根据电源是否断电来禁用时钟信号，延迟监视器用于延迟外部时钟;相位检测器，用于检测相位差 在内部时钟和延迟监视器的输出之间产生检测信号，根据控制信号禁用相位检测器，以及用于根据来自相位检测器的检测信号控制延迟线的移位寄存器。 因此，可以在断电状态下减少整个半导体器件的电流消耗而充分满足功率下降激励时间。

公开(公告)号：US20050093599A1

公开(公告)日：2005-05-05

申请号：US10978623

申请日：2004-11-01

申请人： Jong Tae Kwak

发明人： Jong Tae Kwak

IPC分类号： H03L7/081 ,  G11C5/00 ,  G11C11/407 ,  G11C11/4076 ,  H03L7/06 ,  H03L7/08 ,  H03L7/089

CPC分类号： H03L7/0814 ,  H03L7/0802 ,  H03L7/089

摘要： Disclosed are a delay locked loop (DLL) and a method of driving the same. The delay locked loop includes a clock buffer for buffering an inputted external clock to generate an internal clock, the clock buffer generating a control signal for disabling the internal clock depending on whether the power is down, a delayed line for delaying the internal clock, a clock driver for buffering the output of the delayed line to generate a clock signal, the clock driver disabling the clock signal depending on whether the power is down, a delay monitor for delaying the external clock, a phase detector for detecting the difference in a phase between the internal clock and the output of the delayed monitor to generate a detected signal, the phase detector being disabled according to the control signal, and a shift register for controlling the delayed line according to the detected signal from the phase detector. Therefore, it is possible to sufficiently satisfy power down excitation time while reducing current consumption of the entire semiconductor device during the power down state.

摘要翻译： 公开了一种延迟锁定环（DLL）及其驱动方法。 所述延迟锁定环包括用于缓冲输入的外部时钟以产生内部时钟的时钟缓冲器，所述时钟缓冲器根据所述电源是否断电产生用于禁止所述内部时钟的控制信号，用于延迟所述内部时钟的延迟线， 时钟驱动器，用于缓冲延迟线的输出以产生时钟信号，时钟驱动器根据电源是否断电来禁用时钟信号，延迟监视器用于延迟外部时钟;相位检测器，用于检测相位差 在内部时钟和延迟监视器的输出之间产生检测信号，根据控制信号禁止相位检测器，以及移位寄存器，用于根据来自相位检测器的检测信号控制延迟线。 因此，可以在断电状态下减少整个半导体器件的电流消耗而充分满足功率下降激励时间。

公开(公告)号：US06825703B1

公开(公告)日：2004-11-30

申请号：US10654498

申请日：2003-09-03

申请人： Jong Tae Kwak

发明人： Jong Tae Kwak

IPC分类号： H03L706

CPC分类号： H03L7/0814 ,  H03L7/0802 ,  H03L7/089

摘要： Disclosed are a delay locked loop (DLL) and a method of driving the same. The delay locked loop includes a clock buffer for buffering an inputted external clock to generate an internal clock, the clock buffer generating a control signal for disabling the internal clock depending on whether the power is down, a delayed line for delaying the internal clock, a clock driver for buffering the output of the delayed line to generate a clock signal, the clock driver disabling the clock signal depending on whether the power is down, a delay monitor for delaying the external clock, a phase detector for detecting the difference in a phase between the internal clock and the output of the delayed monitor to generate a detected signal, the phase detector being disabled according to the control signal, and a shift register for controlling the delayed line according to the detected signal from the phase detector. Therefore, it is possible to sufficiently satisfy power down excitation time while reducing current consumption of the entire semiconductor device during the power down state.

摘要翻译： 公开了一种延迟锁定环（DLL）及其驱动方法。 所述延迟锁定环包括用于缓冲输入的外部时钟以产生内部时钟的时钟缓冲器，所述时钟缓冲器根据所述电源是否断电产生用于禁止所述内部时钟的控制信号，用于延迟所述内部时钟的延迟线， 时钟驱动器，用于缓冲延迟线的输出以产生时钟信号，时钟驱动器根据电源是否断电来禁用时钟信号，延迟监视器用于延迟外部时钟;相位检测器，用于检测相位差 在内部时钟和延迟监视器的输出之间产生检测信号，根据控制信号禁用相位检测器，以及用于根据来自相位检测器的检测信号控制延迟线的移位寄存器。 因此，可以在断电状态下减少整个半导体器件的电流消耗而充分满足功率下降激励时间。

公开(公告)号：US06768361B2

公开(公告)日：2004-07-27

申请号：US10236287

申请日：2002-09-06

申请人： Jong Tae Kwak

发明人： Jong Tae Kwak

IPC分类号： H03L706

CPC分类号： H03L7/089 ,  H03L7/0814

摘要： A clock synchronization circuit using a phase mixer is disclosed. The clock synchronization circuit generates an internal clock signal having a phase between phases of two clock signals generated in two variable delay lines with a predetermined phase difference by using the phase mixer, thereby precisely synchronizing the clock signal. When a shift register for controlling the variable delay line performs a shift operation, the output clock signal from the variable delay line where the shift operation is performed is not inputted to the phase mixer, but the output clock signal from the other variable delay line is inputted to the phase mixer. As a result, jitter elements generated due to the shift operation do not influence the internal clock signal.

摘要翻译： 公开了一种使用相位混合器的时钟同步电路。 时钟同步电路通过使用相位混合器产生具有预定相位差的两个可变延迟线中产生的两个时钟信号的相位之间的相位的内部时钟信号，从而精确地同步时钟信号。 当用于控制可变延迟线的移位寄存器执行移位操作时，来自执行移位操作的可变延迟线的输出时钟信号不输入到相位混频器，而来自另一个可变延迟线的输出时钟信号是 输入到相混合器。 结果，由于移位操作产生的抖动元件不影响内部时钟信号。