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    Clock synchronization circuit having improved jitter property
    1.
    发明授权
    Clock synchronization circuit having improved jitter property 有权
    时钟同步电路具有改善的抖动特性

    公开(公告)号：US06573771B2

    公开(公告)日：2003-06-03

    申请号：US10136304

    申请日：2002-05-02

    申请人： Seong-Hoon Lee ,  Jong Tae Kwak ,  Chang-Ki Kwon

    发明人： Seong-Hoon Lee ,  Jong Tae Kwak ,  Chang-Ki Kwon

    IPC分类号： H03L706

    CPC分类号： H03L7/089 ,  H03L7/0814

    摘要： A clock synchronization circuit. The clock synchronization circuit composed of a digital DLL outputs a clock signal delayed by a variable delay line and a clock signal delayed by an additional delay cell, mixes the two clock signals, and outputs an internal clock signal having a smaller delay than a delay time of a delay cell, thereby rapidly precisely synchronizing an external clock signal and the internal clock signal. In addition, a driving unit and a control unit for adjusting a duty cycle are provided to set up a ratio of 50%, thereby improving operation performance.

    摘要翻译： 时钟同步电路。 由数字DLL组成的时钟同步电路输出延迟了可变延迟线的时钟信号和延迟了附加延迟单元的时钟信号，混合两个时钟信号，并输出延迟时间比延迟时间小的内部时钟信号 延迟单元，从而快速精确地同步外部时钟信号和内部时钟信号。 此外，提供用于调整占空比的驱动单元和控制单元以设定50％的比率，从而提高操作性能。

    Delay locked loop device
    3.
    发明授权
    Delay locked loop device 有权
    延迟锁定环路设备

    公开(公告)号：US06956418B2

    公开(公告)日：2005-10-18

    申请号：US10749426

    申请日：2003-12-31

    申请人： Jong-Tae Kwak ,  Seong-Hoon Lee

    发明人： Jong-Tae Kwak ,  Seong-Hoon Lee

    IPC分类号： H03K5/05 ,  G11C11/407 ,  H03L7/06 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087

    CPC分类号： H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

    摘要： A delay locked loop device includes a first delay line for receiving an external clock signal and a first delay control signal to generate a first internal clock signal; a second delay line for receiving the external clock signal and a second delay control signal or the first delay control signal to generate a second internal clock signal; a first delay control block for receiving the external clock signal to generate the first delay control signal; a second delay control block for receiving the external clock signal to generate the second delay control signal; and a phase detecting block for receiving the first internal clock signal and the second internal clock signal to generate the on-off signal by comparing a phase of the first internal clock signal with a phase of the second internal clock signal.

    摘要翻译： 延迟锁定环路装置包括用于接收外部时钟信号的第一延迟线和产生第一内部时钟信号的第一延迟控制信号; 用于接收外部时钟信号的第二延迟线和第二延迟控制信号或第一延迟控制信号以产生第二内部时钟信号; 第一延迟控制块，用于接收外部时钟信号以产生第一延迟控制信号; 第二延迟控制块，用于接收外部时钟信号以产生第二延迟控制信号; 以及相位检测块，用于通过将第一内部时钟信号的相位与第二内部时钟信号的相位进行比较来接收第一内部时钟信号和第二内部时钟信号以产生开关信号。

    CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD
    5.
    发明申请
    CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD 有权
    具有无源负载的电流模式感测放大器

    公开(公告)号：US20110235450A1

    公开(公告)日：2011-09-29

    申请号：US12732968

    申请日：2010-03-26

    申请人： Seong-Hoon Lee ,  Onegyun Na ,  Jongtae Kwak

    发明人： Seong-Hoon Lee ,  Onegyun Na ,  Jongtae Kwak

    IPC分类号： G11C7/06

    CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C2207/063

    摘要： Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

    摘要翻译： 公开了一种存储器，电流模式读出放大器及其操作方法，包括一个包括交叉耦合的p沟道晶体管和耦合到交叉耦合的p沟道晶体管的负载电路的电流模式读出放大器。 负载电路被配置为提供至少部分地控制电流模式读出放大器的环路增益的电阻，负载电路至少包括被动电阻。

    Off-chip driver apparatus, systems, and methods
    6.
    发明授权
    Off-chip driver apparatus, systems, and methods 有权
    片外驱动装置，系统和方法

    公开(公告)号：US07538572B2

    公开(公告)日：2009-05-26

    申请号：US11854973

    申请日：2007-09-13

    申请人： Seong-Hoon Lee

    发明人： Seong-Hoon Lee

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/01721 ,  H03K19/0005

    摘要： Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to an output of the off-chip driver to provide additional initial drive emphasis strength when both transistors are energized for an initial period of time. The time period may be set by an inverted delay circuit.

    摘要翻译： 装置，方法和系统包括具有与片外驱动器并联耦合的输出驱动器的片外驱动器，以在一段时间内提供初始驱动强调。 输出驱动器可以包括耦合到片外驱动器的输出的第一晶体管和第二晶体管，以在两个晶体管在初始时间段通电时提供附加的初始驱动强度强度。 该时间段可以由反相延迟电路设置。

    Synchronous memory device having advanced data align circuit
    7.
    发明授权
    Synchronous memory device having advanced data align circuit 失效
    具有高级数据对准电路的同步存储器件

    公开(公告)号：US07287143B2

    公开(公告)日：2007-10-23

    申请号：US10750602

    申请日：2003-12-29

    申请人： Seong-Hoon Lee ,  Young-Jin Yoon

    发明人： Seong-Hoon Lee ,  Young-Jin Yoon

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1087 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/107

    摘要： A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in response to N−1 number of the align control signals for receiving N-bit data and outputting the N-bit data in a parallel fashion; and a outputting block in response to the remaining align control signal for receiving the N-bit data in the parallel fashion and synchronizing the N-bit data with the remaining align control signal having a N/2 external clock period to thereby generating the synchronized N-bit data as a prefetched data.

    摘要翻译： 一种用于执行N位预取操作的半导体器件，N是正整数，包括：数据选通缓冲装置，用于根据数据选通信号和外部时钟信号产生N个校准控制信号; 响应于N-1个对准控制信号的接收块，用于接收N位数据并以并行方式输出N位数据; 以及响应于用于以并行方式接收N位数据的剩余对准控制信号的输出块，并且使N位数据与具有N / 2个外部时钟周期的剩余对准控制信号同步，从而产生同步N 位数据作为预取数据。

    Method of producing balanced data output
    8.
    发明申请
    Method of producing balanced data output 有权
    产生平衡数据输出的方法

    公开(公告)号：US20060244492A1

    公开(公告)日：2006-11-02

    申请号：US11114130

    申请日：2005-04-26

    申请人： Seong-Hoon Lee

    发明人： Seong-Hoon Lee

    IPC分类号： H03K5/22

    CPC分类号： H03K5/04 ,  H03K5/135 ,  H03K5/26

    摘要： Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then transmits the UP or DOWN control signal to edge adjusting circuits connected to each strobe and data stream between the flip flop and pre-driver. The edge adjusting then adds a delay to each respective strobe and data stream which incrementally compensates for the mismatch created by PVT variations. The process is repeated until the high and low data outputs are effectively matched, thereby maximizing the data eye.

    摘要翻译： 选通信号耦合到相位检测器，该相位检测器比较各个选通信号的上升沿和下降沿。 如果相位检测器确定存在不匹配，则向控制电路输出UP或DOWN控制信号。 然后，控制电路将UP或DOWN控制信号发送到连接到每个选通脉冲的边缘调整电路和触发器和预驱动器之间的数据流。 边缘调整然后对每个相应的选通和数据流添加一个延迟，增量地补偿由PVT变化产生的失配。 重复该过程，直到高和低数据输出被有效地匹配，从而使数据眼睛最大化。

    Digital delay-locked loop circuits with hierarchical delay adjustment
    9.
    发明授权
    Digital delay-locked loop circuits with hierarchical delay adjustment 有权
    具有分层延迟调整的数字延迟锁定环路

    公开(公告)号：US07129761B2

    公开(公告)日：2006-10-31

    申请号：US11256215

    申请日：2005-10-21

    申请人： Seong-Hoon Lee

    发明人： Seong-Hoon Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814

    摘要： Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

    摘要翻译： 微调信号相位调整由多个级联相位混频器提供。 每个相位混合器输出具有其两个输入信号的相位之间的相位的信号。 对于相位混合器的每个后续阶段，相位混合器产生的信号具有较小的相位差，从而提供更好的延迟调整。 可以在数字延迟锁定环路电路中提供多级相位混频器，以提供额外的分层延迟调整。

    Clock generating circuit with multiple modes of operation
    10.
    发明申请
    Clock generating circuit with multiple modes of operation 有权
    具有多种工作模式的时钟发生电路

    公开(公告)号：US20060176761A1

    公开(公告)日：2006-08-10

    申请号：US11054885

    申请日：2005-02-09

    申请人： Seong-Hoon Lee

    发明人： Seong-Hoon Lee

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/095 ,  H03L7/0995

    摘要： A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding o the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.

    摘要翻译： 时钟发生电路包括相位比较电路，该相位比较电路产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。