公开(公告)号：US20060113590A1

公开(公告)日：2006-06-01

申请号：US11285558

申请日：2005-11-22

申请人： Ji-Hae Kim ,  Ji-Young Kim ,  Jong-Chul Park ,  Yong-Sun Ko ,  Sang-Sup Jeong

发明人： Ji-Hae Kim ,  Ji-Young Kim ,  Jong-Chul Park ,  Yong-Sun Ko ,  Sang-Sup Jeong

IPC分类号： H01L29/94

CPC分类号： H01L29/66621 ,  H01L29/7834

摘要： An isolation layer having a first depth is formed from an upper face of a substrate. Source/drain regions including junctions are formed in the substrate. Each of the junctions has a second depth substantially smaller than the first depth. A first recess is formed in the substrate by a first etching process. A protection layer pattern is formed on a sidewall of the first recess. A second recess is formed beneath the first recess. The second recess has a width substantially larger than that of the first recess. The second recess is formed by a second etching process using an etching gas containing an SF6 gas, a Cl2 gas and an O2 gas. A gate insulation layer is formed on surfaces of the first and the second recesses. The second recess having an enlarged shape may reduce a width of the junction between the gate electrode and the isolation layer so that a leakage current generated through the junction may decrease.

摘要翻译： 具有第一深度的隔离层由衬底的上表面形成。 在衬底中形成包括结的源/漏区。 每个结点具有比第一深度基本上小的第二深度。 通过第一蚀刻工艺在衬底中形成第一凹部。 在第一凹部的侧壁上形成保护层图案。 在第一凹部下面形成第二凹部。 第二凹部的宽度显着大于第一凹部的宽度。 第二凹槽通过使用含有SF 6气体，Cl 2气体和O 2气体的蚀刻气体的第二蚀刻工艺形成 。 在第一和第二凹部的表面上形成栅极绝缘层。 具有放大形状的第二凹部可以减小栅电极和隔离层之间的结的宽度，使得通过结可以产生的漏电流可能减小。

公开(公告)号：US07091117B2

公开(公告)日：2006-08-15

申请号：US10836694

申请日：2004-04-30

申请人： Jae-Woo Kim ,  Yong-Sun Ko ,  Sang-Sup Jeong

发明人： Jae-Woo Kim ,  Yong-Sun Ko ,  Sang-Sup Jeong

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66553 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823437 ,  H01L27/10873

摘要： A method of fabricating a semiconductor device including sequentially forming a polysilicon layer, a first insulating layer, and a photoresist layer over a gate oxide film positioned on a semiconductor substrate. A photoresist pattern with a first groove is formed by selectively patterning the photoresist layer to partially expose a surface of the first insulating layer. A second insulating layer is formed over the photoresist pattern with the first groove and over the exposed surface of the first insulating layer. A sacrificial spacer is formed on each inner wall of the first groove by etching back the second insulating layer and forming a second groove in the first insulating layer in communication with the first groove to expose a surface of the polysilicon layer at the bottom of the second groove. The photoresist pattern is removed, and an arbitrary layer pattern is formed over the polysilicon layer at the bottom of the second groove. The sacrificial spacers and first insulating layer are removed, and a gate electrode is formed by etching the polysilicon layer using the arbitrary layer pattern as a mask.

摘要翻译： 一种制造半导体器件的方法，包括在位于半导体衬底上的栅极氧化膜上顺序地形成多晶硅层，第一绝缘层和光致抗蚀剂层。 通过选择性地图案化光致抗蚀剂层以部分地暴露第一绝缘层的表面来形成具有第一凹槽的光刻胶图案。 在光致抗蚀剂图案上形成有第一绝缘层和第一绝缘层的暴露表面上的第一绝缘层。 通过蚀刻第二绝缘层并在与第一凹槽连通的第一绝缘层中形成第二凹槽，在第二凹槽的每个内壁上形成牺牲隔离物，以暴露第二凹槽底部的多晶硅层的表面 槽。 去除光致抗蚀剂图案，并且在第二凹槽底部的多晶硅层上形成任意层图案。 去除牺牲间隔物和第一绝缘层，并且通过使用任意层图案作为掩模蚀刻多晶硅层来形成栅电极。

公开(公告)号：US07534726B2

公开(公告)日：2009-05-19

申请号：US11682632

申请日：2007-03-06

申请人： Jong-Chul Park ,  Yong-Sun Ko ,  Tae-Hyuk Ahn

发明人： Jong-Chul Park ,  Yong-Sun Ko ,  Tae-Hyuk Ahn

IPC分类号： H01L21/311

CPC分类号： H01L29/66621 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/10808 ,  H01L27/10876

摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.

摘要翻译： 提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。 掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。 使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。 掩模层可以被图案化为曲线型。 在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。 然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

公开(公告)号：US07205199B2

公开(公告)日：2007-04-17

申请号：US10917615

申请日：2004-08-13

申请人： Jong-Chul Park ,  Yong-Sun Ko ,  Tae-Hyuk Ahn

发明人： Jong-Chul Park ,  Yong-Sun Ko ,  Tae-Hyuk Ahn

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/10808 ,  H01L27/10876

摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.

摘要翻译： 提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。 掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。 使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。 掩模层可以被图案化为曲线型。 在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。 然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

公开(公告)号：US20050077568A1

公开(公告)日：2005-04-14

申请号：US10917615

申请日：2004-08-13

申请人： Jong-Chul Park ,  Yong-Sun Ko ,  Tae-Hyuk Ahn

发明人： Jong-Chul Park ,  Yong-Sun Ko ,  Tae-Hyuk Ahn

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/76 ,  H01L21/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66621 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/10808 ,  H01L27/10876

摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.

摘要翻译： 提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。 掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。 使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。 掩模层可以被图案化为曲线型。 在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。 然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

公开(公告)号：US08084801B2

公开(公告)日：2011-12-27

申请号：US12654255

申请日：2009-12-15

申请人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

发明人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/10888

摘要： In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

摘要翻译： 在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。 位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。 位线可以与第三区域的位线接触焊盘连接。 尽管6F2结构的单元电池，电池结构也可以更容易地形成。 多个有源区域可以具有包括主轴和短轴的椭圆形状。 多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心 相邻活动行中的区域。

公开(公告)号：US08053751B2

公开(公告)日：2011-11-08

申请号：US12591531

申请日：2009-11-23

申请人： Tae-Won Kim ,  Yong-Sun Ko ,  Ki-Jong Park ,  Kyung-Hyun Kim

发明人： Tae-Won Kim ,  Yong-Sun Ko ,  Ki-Jong Park ,  Kyung-Hyun Kim

IPC分类号： H01L21/4763

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

摘要翻译： 在相变半导体器件及其制造方法中，示例性方法可以包括在衬底上形成金属层图案，金属层图案包括露出衬底的一部分的开口，在其上形成蚀刻停止层 金属层图案，开口的侧壁和衬底的暴露部分，蚀刻停止层形成为具有小于上部厚度阈值的厚度，以及减少至少一部分蚀刻停止层，蚀刻部分的蚀刻 停止层与基底形成电连接。

公开(公告)号：US08048809B2

公开(公告)日：2011-11-01

申请号：US11898850

申请日：2007-09-17

申请人： Hyo-Jin Lee ,  Kyung-Hyun Kim ,  Yong-Sun Ko

发明人： Hyo-Jin Lee ,  Kyung-Hyun Kim ,  Yong-Sun Ko

IPC分类号： H01L21/302

CPC分类号： H01L21/7684 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/28123 ,  H01L21/3212

摘要： A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.

摘要翻译： 浆料组合物包括约4.25至约18.5重量％的研磨剂，约80至约95重量％的去离子水和约0.05至约1.5重量％的添加剂。 浆料组合物还可以包括表面活性剂。 在使用浆料组合物的抛光方法中，可以快速抛光多晶硅层，并且可以抑制多晶硅层的凹陷和侵蚀。

公开(公告)号：US07781346B2

公开(公告)日：2010-08-24

申请号：US11455815

申请日：2006-06-20

申请人： Cheol-Woo Park ,  Byoung-Moon Yoon ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Kwang-Wook Lee

发明人： Cheol-Woo Park ,  Byoung-Moon Yoon ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Kwang-Wook Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/31111 ,  H01L21/0206 ,  H01L21/02068 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.

摘要翻译： 可以通过使用含有蚀刻剂的湿法蚀刻工艺形成半导体结构。 半导体结构可以包括具有增加的或更高的纵横比的多个图案，并且可以彼此更靠近地布置。 可以在半导体结构上使用氟化氢气体进行干法处理。

公开(公告)号：US20100072446A1

公开(公告)日：2010-03-25

申请号：US12591531

申请日：2009-11-23

申请人： Tae-Won Kim ,  Yong-Sun Ko ,  Ki-Jong Park ,  Kyung-Hyun Kim

发明人： Tae-Won Kim ,  Yong-Sun Ko ,  Ki-Jong Park ,  Kyung-Hyun Kim

IPC分类号： H01L45/00 ,  H01L21/768

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

摘要翻译： 在相变半导体器件及其制造方法中，示例性方法可以包括在衬底上形成金属层图案，金属层图案包括露出衬底的一部分的开口，在其上形成蚀刻停止层 金属层图案，开口的侧壁和衬底的暴露部分，蚀刻停止层形成为具有小于上部厚度阈值的厚度，以及减少至少一部分蚀刻停止层，蚀刻部分的蚀刻 停止层与基底形成电连接。