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公开(公告)号：US09317360B2
公开(公告)日：2016-04-19
申请号：US13995458
申请日：2011-12-29
申请人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
发明人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
CPC分类号： G06F11/1004 , G06F11/0724 , G06F11/0793
摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.
摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。
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公开(公告)号：US20130339829A1
公开(公告)日：2013-12-19
申请号：US13995458
申请日：2011-12-29
申请人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
发明人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , G06F11/0724 , G06F11/0793
摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.
摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。
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公开(公告)号：US20180189081A1
公开(公告)日：2018-07-05
申请号：US15396077
申请日：2016-12-30
申请人： Neeraj S. Upasani , Jeanne Guillory , Wojciech Powiertowski , Sergiu D Ghetie , Mohan J. Kumar , Murugasamy K. Nachimuthu
发明人： Neeraj S. Upasani , Jeanne Guillory , Wojciech Powiertowski , Sergiu D Ghetie , Mohan J. Kumar , Murugasamy K. Nachimuthu
IPC分类号： G06F9/445 , H04L12/933 , H04L12/24 , G06F9/44 , G06F15/78
CPC分类号： G06F9/44521 , G06F8/654 , G06F9/4401 , G06F15/7807 , G06F15/7867 , H04L41/0813 , H04L41/5054 , H04L41/5096 , H04L49/109
摘要： Dynamically configurable server platforms and associated apparatus and methods. A server platform including a plurality of CPUs installed in respective sockets may be dynamically configured as multiple single-socket servers and as a multi-socket server. The CPUs are connected to a platform manager component comprising an SoC including one or more processors and an embedded FPGA. Following a platform reset, an FPGA image is loaded, dynamically configuring functional blocks and interfaces on the platform manager. The platform manager also includes pre-defined functional blocks and interfaces. During platform initialization the dynamically-configured functional blocks and interfaces are used to initialize the server platform, while both the pre-defined and dynamically-configured functional blocks and interfaces are used to support run-time operations. The server platform may be used in conventional rack architectures or implemented in a disaggregated rack architecture under which the single-socket and/or multi-socket servers are dynamically composed to employ disaggregated resources, such as memory, storage, and accelerators.
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公开(公告)号：US20150378808A1
公开(公告)日：2015-12-31
申请号：US14319387
申请日：2014-06-30
IPC分类号： G06F11/07
CPC分类号： G06F11/073 , G06F11/0769 , G06F11/0787 , G09C1/00 , G11C5/04 , G11C29/52 , G11C2029/0409
摘要： Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.
摘要翻译： 示例可以包括用于与用于非易失性双列直插式存储器模块（NVDIMM）的控制器通信的计算平台的基本输入/输出系统（BIOS）。 BIOS和控制器之间的通信可以包括控制器在NVDIMM下扫描和识别非易失性存储器中的错误位置的请求。 非易失性存储器可能能够为NVDIMM提供持久存储器。
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5.发明申请ENHANCED SYSTEM SLEEP STATE SUPPORT IN SERVERS USING NON-VOLATILE RANDOM ACCESS MEMORY 有权使用非易失性随机访问存储器的服务器中的增强系统休眠状态支持公开(公告)号：US20130290759A1
公开(公告)日：2013-10-31
申请号：US13976901
申请日：2011-12-13
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3275 , G06F1/3287 , G06F9/4418 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.
摘要翻译： 在计算机系统中使用非易失性随机存取存储器（NVRAM）来增强对睡眠状态的支持。 计算机系统包括处理器，可字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）和电源管理（PM）模块。 动态随机存取存储器（DRAM）提供系统地址空间的一部分。 PM模块拦截由操作系统启动进入休眠状态的请求，将数据从DRAM复制到NVRAM，将系统地址空间的一部分映射到NVRAM，并将DRAM转换为 睡眠状态。 在发生唤醒事件时，PM模块向操作系统返回控制，使得计算机系统恢复工作状态操作，而操作系统不知道系统地址空间的一部分已经映射到NVRAM。
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公开(公告)号：US10331614B2
公开(公告)日：2019-06-25
申请号：US15025988
申请日：2013-11-27
申请人： INTEL CORPORATION , Dimitrios Ziakas , Bassam N. Coury , Mohan J. Kumar , Murugasamy K. Nachimuthu , Thi Dang , Russell J. Wunderlich
发明人： Dimitrios Ziakas , Bassam N. Coury , Mohan J. Kumar , Murugasamy K. Nachimuthu , Thi Dang , Russell J. Wunderlich
摘要： Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
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7.发明申请公开(公告)号：US20180034909A1
公开(公告)日：2018-02-01
申请号：US15221707
申请日：2016-07-28
摘要： Mechanisms for efficient discovery of storage resources in a Rack Scale Architecture (RSA) system and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage drawers communicatively coupled via input-output (IO) cables. Compute nodes including one or more processors, memory resources, and optional local storage resources are installed in the pooled compute drawers, and are enabled to be selectively-coupled to storage resources in the pooled storage drawers over virtual attachment links. During a discovery process, a compute node determines storage resource characteristics of storage resources it may be selectively-coupled to and the attachment links used to access the storage resources. The storage resource characteristics are aggregated by a pod manager that uses corresponding configuration information to dynamically compose compute nodes for rack users based on user needs.
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公开(公告)号：US20110179311A1
公开(公告)日：2011-07-21
申请号：US12971868
申请日：2010-12-17
IPC分类号： G06F11/00
CPC分类号： G06F11/3676
摘要： In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，接收到执行错误注入或存储器迁移的请求，输入阻止来自除当前处理器核心或线程以外的代理的请求的模式，注入错误或存储器迁移的模式以及阻止 来自除当前处理器核心或线程之外的代理的请求退出。 描述和要求保护其他实施例。
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公开(公告)号：US20170289256A1
公开(公告)日：2017-10-05
申请号：US15089377
申请日：2016-04-01
IPC分类号： H04L29/08 , H04L29/06 , H04L12/24 , H04L12/46 , H04L12/931
CPC分类号： H04L67/125 , G06F1/20 , H04L12/4641 , H04L41/0668 , H04L41/0695 , H04L41/12 , H04L43/08 , H04L43/0817 , H04L43/10 , H04L49/70 , H04L63/08 , H04L67/02 , H04L67/10 , H04L67/1095 , H04L67/1097 , H04L67/12 , H04L69/40
摘要： Methods and apparatus for highly available rack management in Rack Scale environment. Rack Management Modules (RMMs) are configured to manage power and thermal zones in a rack including a plurality of pooled system drawers, wherein each pooled system drawer is associated with a respective power zone including power sensors and power control devices and a respective thermal zone including thermal sensors and thermal devices. During operation, one of the RMMs is implemented as a master RMM, and the other is implemented as a slave RMM. The master RMM is used to monitor the power and thermal zones. State information is periodically synchronized between the master RMM and the slave RMM. The RMMs are further configured to perform a fail-over operation in connection with a failed or failing RMM, where after the fail-over operation the slave becomes the new master RMM and the previous master RMM becomes the new slave.
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10.发明授权公开(公告)号：US10791174B2
公开(公告)日：2020-09-29
申请号：US15221707
申请日：2016-07-28
摘要： Mechanisms for efficient discovery of storage resources in a Rack Scale Architecture (RSA) system and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage drawers communicatively coupled via input-output (IO) cables. Compute nodes including one or more processors, memory resources, and optional local storage resources are installed in the pooled compute drawers, and are enabled to be selectively-coupled to storage resources in the pooled storage drawers over virtual attachment links. During a discovery process, a compute node determines storage resource characteristics of storage resources it may be selectively-coupled to and the attachment links used to access the storage resources. The storage resource characteristics are aggregated by a pod manager that uses corresponding configuration information to dynamically compose compute nodes for rack users based on user needs.
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