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公开(公告)号：US08476601B1
公开(公告)日：2013-07-02
申请号：US12004968
申请日：2007-12-20
IPC分类号： G01N23/00
CPC分类号： G01N23/222 , G01N2223/6113
摘要： Systems and methods are provided for identifying an atomic element in proximity to an integrated circuit. Trace amounts of a contaminant are identifiable. The atomic element is exposed to neutron radiation to convert a portion of the atomic element into a radioactive isotope of the atomic element. Upsets are measured for the binary states of the memory cells of the integrated circuit during a time period following the exposure to the neutron radiation. The atomic element is identified from the upsets of the binary states of the memory cells of the integrated circuit.
摘要翻译： 提供了用于识别靠近集成电路的原子元件的系统和方法。 痕量的污染物是可识别的。 原子元素暴露于中子辐射以将原子元素的一部分转化为原子元素的放射性同位素。 在暴露于中子辐射之后的一段时间内，对集成电路的存储单元的二进制状态进行测量。 根据集成电路的存储单元的二进制状态的不匹配来识别原子元素。
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2.发明授权Determining a characteristic of atomic particles affecting a programmable logic device 有权确定影响可编程逻辑器件的原子粒子的特性公开(公告)号：US07763861B1
公开(公告)日：2010-07-27
申请号：US11975972
申请日：2007-10-23
IPC分类号： G01T3/00
CPC分类号： H03K19/17764
摘要： Methods and systems are provided for determining a characteristic of an atomic particle affecting a programmable logic device (PLD). The PLD is configured to generate a value at one or more outputs. A source generates a packet of atomic particles. The departure from the source is indicated for the packet of the atomic particles. The PLD is impacted with the packet of the atomic particles. A change is detected in the value of one or more outputs of the PLD. The change in the value of the output or outputs is a result of the impact of the PLD by one of the atomic particles from the packet. A time interval is determined between the departure of the packet of the atomic particles from the source and the change in the value of the output or outputs.
摘要翻译： 提供了用于确定影响可编程逻辑器件（PLD）的原子粒子的特性的方法和系统。 PLD被配置为在一个或多个输出处产生一个值。 源产生一个原子粒子包。 对于原子粒子的包，指示源的偏离。 PLD受到原子粒子的包的影响。 在PLD的一个或多个输出的值中检测到变化。 输出或输出值的变化是PLD受到数据包中原子粒子之一的影响的结果。 在来自源的原子粒子的分组的离开与输出或输出的值的变化之间确定时间间隔。
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3.发明授权Single event upset in SRAM cells in FPGAs with high resistivity gate structures 有权在具有高电阻率栅极结构的FPGA中的SRAM单元中的单事件不正常公开(公告)号：US07452765B1
公开(公告)日：2008-11-18
申请号：US11242409
申请日：2005-09-30
申请人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
发明人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
IPC分类号： H01L21/8238
CPC分类号： H01L27/11803 , H01L21/76831 , H01L21/76834 , H01L27/11
摘要： SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
摘要翻译： SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。 对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。 对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。
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4.发明授权Single event upset in SRAM cells in FPGAs with high resistivity gate structures 有权在具有高电阻率栅极结构的FPGA中的SRAM单元中的单事件不正常公开(公告)号：US06982451B1
公开(公告)日：2006-01-03
申请号：US10402446
申请日：2003-03-27
申请人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
发明人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
IPC分类号： H01L27/108
CPC分类号： H01L27/11803 , H01L21/76831 , H01L21/76834 , H01L27/11
摘要： SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
摘要翻译： SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。 对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。 对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。
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公开(公告)号：US07619486B1
公开(公告)日：2009-11-17
申请号：US11715534
申请日：2007-03-07
申请人： Austin H. Lesea
发明人： Austin H. Lesea
IPC分类号： H03L1/04
摘要： An integrated circuit fabricated in a multiple oxide process can be used to provide a temperature-insensitive circuit. The temperature-insensitive circuit can be a ring oscillator; this ring oscillator can be used as a low-cost integrated reference frequency to monitor and to modify the behavior of the integrated to produce the desired results. In some embodiments, the reference oscillator output can be compared to second oscillator output where the second oscillator performance is temperature-sensitive. The comparison result can be monitored and processed to power down the integrated circuit.
摘要翻译： 可以使用以多重氧化物工艺制造的集成电路来提供温度不敏感的电路。 温度不敏感电路可以是环形振荡器; 该环形振荡器可以用作低成本的集成参考频率来监视和修改集成的行为以产生期望的结果。 在一些实施例中，可以将参考振荡器输出与第二振荡器输出进行比较，其中第二振荡器性能是温度敏感的。 可以对比较结果进行监控和处理，以使集成电路断电。
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6.发明授权Method and apparatus for generating a phase locked spread spectrum clock signal 有权用于产生锁相扩频时钟信号的方法和装置公开(公告)号：US07254157B1
公开(公告)日：2007-08-07
申请号：US10109130
申请日：2002-03-27
申请人： Patrick J. Crotty , Austin H. Lesea
发明人： Patrick J. Crotty , Austin H. Lesea
CPC分类号： H03K3/84
摘要： A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.
摘要翻译： 提供了一种在集成电路上产生扩频时钟信号的方法和装置。 可以通过改变环形振荡器的电源电压来调制由环形振荡器产生的目标频率，从而改变目标频率。 在一个实施例中，电源电压由可被数字控制的模拟多路复用器产生。 固定电压源可以向模拟多路复用器提供输入信号。 在一个实施例中，固定电压源可以用单位增益放大器来实现。
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7.发明授权Routing with derivative frame awareness to minimize device programming time and test cost 有权具有派生框架意识的路由，以最小化设备编程时间和测试成本公开(公告)号：US07240320B1
公开(公告)日：2007-07-03
申请号：US10989679
申请日：2004-11-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.
摘要翻译： 在可编程逻辑器件（PLD）上实现设计的方法包括生成识别PLD的资源和编程帧之间的对应关系的数据库。 编译第一PLD设计，其中第一设计以第一方式使用第一组资源。 降低了以第一种方式使用第一种设计的第一组资源相关联的成本。 然后编制第二PLD设计，应用与使用第一组资源相关联的降低的成本。 识别编译第二设计所需的第二组资源，其中第二组资源不以与第一组资源相同的方式使用。 识别与第二组资源相关联的一组编程帧。 与使用与该组编程帧相关联的第三组资源相关联的成本增加。
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公开(公告)号：US07062692B1
公开(公告)日：2006-06-13
申请号：US10255502
申请日：2002-09-26
申请人： Austin H. Lesea
发明人： Austin H. Lesea
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31726
摘要： Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be provided to a wafer prober or integrated circuit tester to determine whether duty cycle is within an acceptance range. Alternatively, the duty cycle indicator signal may be provided to drive adjustment circuitry. In response to duty cycle not being within an acceptance range, drive adjust circuitry provides a drive adjustment signal to adjust duty cycle at an output buffer by turning on one or more p-channel drive transistors, one or more n-channel drive transistors, or a combination of both. Moreover, wells may be biased responsive to a detected duty cycle in order to correct the duty cycle.
摘要翻译： 描述了用于占空比确定和调整的方法和装置。 更具体地，输出信号被采样并提供给表征采样输出信号的占空比的占空比检查电路。 该表征可以提供给晶片探测器或集成电路测试器，以确定占空比是否在接受范围内。 或者，占空比指示信号可以被提供给驱动调整电路。 响应于占空比不在允许范围内，驱动调节电路提供驱动调节信号，以通过接通一个或多个p沟道驱动晶体管，一个或多个n沟道驱动晶体管或 两者的结合。 此外，孔可以响应于检测到的占空比而被偏置，以便校正占空比。
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公开(公告)号：US06849951B1
公开(公告)日：2005-02-01
申请号：US10377863
申请日：2003-02-28
IPC分类号： H01L23/528 , H01L23/64 , H01L25/065 , H01L23/52
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/5286 , H01L23/642 , H01L24/48 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/12036 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/16152 , H01L2924/19011 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A die having a bypass capacitor is stacked on another die having an active circuit. The active circuit draws a spike of current, for example, during a switching period of a voltage on its output lead from one digital logic level to another digital logic level. The bypass capacitor provides a portion of the spike of current through a conductive plug that extends from a plate of the bypass capacitor to a power lead of the active circuit. The length of the conductive plug is reduced by extending the conductive plug from the bypass capacitor to the active circuit orthogonally to the planar orientation of the dice. Reducing the length of the conductive plug reduces the resistance and inductance of the conductive plug and, in turn, reduces the drop in voltage between the voltage on the bypass capacitor and the voltage on the power lead of the active circuit.
摘要翻译： 具有旁路电容器的管芯堆叠在具有有源电路的另一管芯上。 有源电路例如在其输出引线上的电压从一个数字逻辑电平到另一数字逻辑电平的开关周期期间画出电流尖峰。 旁路电容器通过从旁路电容器的板延伸到有源电路的电源线的导电插头提供电流尖峰的一部分。 通过将导电插塞从旁路电容器延伸到与裸片的平面取向正交的有源电路，导电插头的长度减小。 降低导电插头的长度会降低导电插头的电阻和电感，进而降低旁路电容器上的电压与有源电路的电源线上的电压之间的电压降。
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公开(公告)号：US06735110B1
公开(公告)日：2004-05-11
申请号：US10125666
申请日：2002-04-17
申请人： Austin H. Lesea
发明人： Austin H. Lesea
IPC分类号： G11C1100
CPC分类号： G11C11/4125
摘要： Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.
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