公开(公告)号：US20130026465A1

公开(公告)日：2013-01-31

申请号：US13194980

申请日：2011-07-31

申请人： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

发明人： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7845

摘要： A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

摘要翻译： 具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点， 分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。

公开(公告)号：US08877593B2

公开(公告)日：2014-11-04

申请号：US13194980

申请日：2011-07-31

申请人： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

发明人： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/66

CPC分类号： H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7845

摘要： A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

摘要翻译： 具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点， 分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。

公开(公告)号：US20110309334A1

公开(公告)日：2011-12-22

申请号：US12820341

申请日：2010-06-22

申请人： Josephine Chang ,  Isaac Lauer ,  Jeffrey Sleight

发明人： Josephine Chang ,  Isaac Lauer ,  Jeffrey Sleight

IPC分类号： H01L29/78 ,  H01L29/76 ,  H01L21/84

CPC分类号： H01L29/66628 ,  B82Y10/00 ,  H01L21/76897 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0508

摘要： A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

摘要翻译： 一种用于形成场效应晶体管（FET）的方法，包括在衬底上沉积沟道材料，所述沟道材料包括石墨烯或纳米结构之一; 在所述通道材料的第一部分上形成栅极; 形成邻近门的间隔物; 在沟道材料，栅极和间隔物上沉积接触材料; 在所述接触材料上沉积介电材料; 去除介电材料的一部分和接触材料的一部分以暴露栅极的顶部; 使接触材料凹陷; 去除介电材料; 以及图案化所述接触材料以形成所述FET的自对准接触，所述自对准接触位于所述FET的源极区域和漏极区域之上，所述源极区域和所述漏极区域包括所述沟道材料的第二部分 。

公开(公告)号：US20120298949A1

公开(公告)日：2012-11-29

申请号：US13570275

申请日：2012-08-09

申请人： Josephine Chang ,  Isaac Lauer ,  Jeffrey Sleight

发明人： Josephine Chang ,  Isaac Lauer ,  Jeffrey Sleight

IPC分类号： H01L29/10

CPC分类号： H01L29/66628 ,  B82Y10/00 ,  H01L21/76897 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0508

摘要： A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

摘要翻译： 场效应晶体管（FET）包括衬底; 位于所述基板上的通道材料，所述通道材料包括石墨烯或纳米结构之一; 位于所述通道材料的第一部分上的门; 以及与栅极对准的触点，所述触点包括金属硅化物，金属碳化物和金属之一，所述触点位于所述FET的源极区域和漏极区域之上，所述源极区域和所述漏极区域包括 通道材料的第二部分。

公开(公告)号：US09368599B2

公开(公告)日：2016-06-14

申请号：US12820341

申请日：2010-06-22

申请人： Josephine Chang ,  Isaac Lauer ,  Jeffrey Sleight

发明人： Josephine Chang ,  Isaac Lauer ,  Jeffrey Sleight

IPC分类号： H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L21/768 ,  H01L29/786 ,  H01L51/05 ,  H01L51/00

CPC分类号： H01L29/66628 ,  B82Y10/00 ,  H01L21/76897 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0508

摘要： A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

摘要翻译： 一种用于形成场效应晶体管（FET）的方法，包括在衬底上沉积沟道材料，所述沟道材料包括石墨烯或纳米结构之一; 在所述通道材料的第一部分上形成栅极; 形成邻近门的间隔物; 在沟道材料，栅极和间隔物上沉积接触材料; 在所述接触材料上沉积介电材料; 去除介电材料的一部分和接触材料的一部分以暴露栅极的顶部; 使接触材料凹陷; 去除介电材料; 以及图案化所述接触材料以形成所述FET的自对准接触，所述自对准接触位于所述FET的源极区域和漏极区域之上，所述源极区域和所述漏极区域包括所述沟道材料的第二部分 。

公开(公告)号：US20140239258A1

公开(公告)日：2014-08-28

申请号：US13571657

申请日：2012-08-10

申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/0847 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S977/723 ,  Y10S977/938

摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

摘要翻译： 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。

公开(公告)号：US08343815B2

公开(公告)日：2013-01-01

申请号：US12777881

申请日：2010-05-11

申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

IPC分类号： H01L29/72

CPC分类号： H01L29/0847 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S977/723 ,  Y10S977/938

摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

公开(公告)号：US08946680B2

公开(公告)日：2015-02-03

申请号：US13571657

申请日：2012-08-10

申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

IPC分类号： H01L29/72 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/0847 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S977/723 ,  Y10S977/938

摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

摘要翻译： 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。

公开(公告)号：US20120299107A1

公开(公告)日：2012-11-29

申请号：US13571734

申请日：2012-08-10

申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

IPC分类号： H01L27/12

CPC分类号： H01L21/823807 ,  H01L29/7847

摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力记忆技术（SMT），栅极硅化物和源极/漏极硅化物区域引起的升高的应力的NFET栅极区域和双重应力衬里，并且其中所述高密度器件 区域包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。

公开(公告)号：US20110278542A1

公开(公告)日：2011-11-17

申请号：US12777881

申请日：2010-05-11

申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey Sleight

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/0847 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S977/723 ,  Y10S977/938

摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.

摘要翻译： 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。