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    High Performance Devices and High Density Devices on Single Chip
    1.
    发明申请
    High Performance Devices and High Density Devices on Single Chip 失效
    单芯片高性能器件和高密度器件

    公开(公告)号：US20120299107A1

    公开(公告)日：2012-11-29

    申请号：US13571734

    申请日：2012-08-10

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    IPC分类号： H01L27/12

    CPC分类号： H01L21/823807 ,  H01L29/7847

    摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

    摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力记忆技术（SMT），栅极硅化物和源极/漏极硅化物区域引起的升高的应力的NFET栅极区域和双重应力衬里，并且其中所述高密度器件 区域包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。

    Structure with reduced fringe capacitance
    2.
    发明授权
    Structure with reduced fringe capacitance 有权
    具有降低的边缘电容的结构

    公开(公告)号：US08247877B2

    公开(公告)日：2012-08-21

    申请号：US12550543

    申请日：2009-08-31

    申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

    IPC分类号： H01L29/78

    CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966

    摘要： A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack.

    摘要翻译： 一种结构包括衬底和设置在衬底上的栅叠层。 该结构还包括设置在栅极堆叠的侧壁上并已经暴露于等离子体源的氮化物封装层。 该结构还包括在氮化物封装层接触栅叠层的侧壁的区域中与氮化物封装层接触的至少一个其它元件。

    High performance devices and high density devices on single chip
    3.
    发明授权
    High performance devices and high density devices on single chip 失效
    单芯片高性能器件和高密度器件

    公开(公告)号：US08686506B2

    公开(公告)日：2014-04-01

    申请号：US13571734

    申请日：2012-08-10

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    IPC分类号： H01L29/72

    CPC分类号： H01L21/823807 ,  H01L29/7847

    摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

    摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力记忆技术（SMT），栅极硅化物和源极/漏极硅化物区域引起的升高的应力的NFET栅极区域和双重应力衬里，并且其中所述高密度器件 区域包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。

    High performance devices and high density devices on single chip
    4.
    发明授权
    High performance devices and high density devices on single chip 失效
    单芯片高性能器件和高密度器件

    公开(公告)号：US08338239B2

    公开(公告)日：2012-12-25

    申请号：US12781896

    申请日：2010-05-18

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    IPC分类号： H01L29/72

    CPC分类号： H01L21/823807 ,  H01L29/7847

    摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

    摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力存储技术（SMT），栅极和源极/漏极硅化物区域以及双重应力衬底引起的升高的应力的NFET栅极区域，并且其中所述高密度器件区域 包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。

    High Performance Devices and High Density Devices on Single Chip
    5.
    发明申请
    High Performance Devices and High Density Devices on Single Chip 失效
    单芯片高性能器件和高密度器件

    公开(公告)号：US20110284962A1

    公开(公告)日：2011-11-24

    申请号：US12781896

    申请日：2010-05-18

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey Sleight

    IPC分类号： H01L27/12 ,  H01L21/782

    CPC分类号： H01L21/823807 ,  H01L29/7847

    摘要： A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

    摘要翻译： 包括高性能器件区域和高密度器件区域的CMOS芯片包括在高性能器件区域中包括n型场效应晶体管（NFET）和p型场效应晶体管（PFET）的多个高性能器件，其中 高性能器件具有高性能间距; 以及在高密度器件区域中包括NFET和PFET的多个高密度器件，其中高密度器件具有高密度间距，并且其中高性能间距是高密度间距的约2至3倍; 其中所述高性能器件区域包括掺杂源极和漏极区域，具有使用应力存储技术（SMT），栅极和源极/漏极硅化物区域以及双重应力衬底引起的升高的应力的NFET栅极区域，并且其中所述高密度器件区域 包括掺杂源极和漏极区，栅极硅化物区域和中性应力衬里。

    STRUCTURE WITH REDUCED FRINGE CAPACITANCE
    6.
    发明申请
    STRUCTURE WITH REDUCED FRINGE CAPACITANCE 有权
    结构与减少的FRINGE电容

    公开(公告)号：US20110049645A1

    公开(公告)日：2011-03-03

    申请号：US12550543

    申请日：2009-08-31

    申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966

    摘要： A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack.

    摘要翻译： 一种结构包括衬底和设置在衬底上的栅叠层。 该结构还包括设置在栅极堆叠的侧壁上并已经暴露于等离子体源的氮化物封装层。 该结构还包括在氮化物封装层与栅叠层的侧壁接触的区域中与氮化物封装层接触的至少一个其它元件。

    Method for fabricating transistor with high-K dielectric sidewall spacer
    7.
    发明授权
    Method for fabricating transistor with high-K dielectric sidewall spacer 有权
    用于制造具有高K电介质侧壁间隔物的晶体管的方法

    公开(公告)号：US08536041B2

    公开(公告)日：2013-09-17

    申请号：US13559182

    申请日：2012-07-26

    申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L27/01

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/78654

    摘要： A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

    摘要翻译： 提供了一种用于制造晶体管的方法。 该晶体管包括一个硅层，该硅层包括一个源区和一个漏极区，一个位于源极区和漏极区之间的硅层上的栅极堆叠，以及设置在栅叠层的侧壁上的侧壁隔离层。 栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。 还提供了制造这种晶体管的方法。

    8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES
    8.
    发明申请
    8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES 有权
    具有外部门极二极管的8晶体管SRAM单元设计

    公开(公告)号：US20130176771A1

    公开(公告)日：2013-07-11

    申请号：US13345636

    申请日：2012-01-06

    申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC分类号： G11C11/40

    CPC分类号： G11C16/24 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

    摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

    摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极 线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same
    9.
    发明申请
    Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same 有权
    具有硅侧壁的金属高K晶体管，用于减少寄生电容，以及制造相同的工艺

    公开(公告)号：US20120187506A1

    公开(公告)日：2012-07-26

    申请号：US13432395

    申请日：2012-03-28

    申请人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    发明人： Leland Chang ,  Jeffrey W. Sleight ,  Isaac Lauer ,  Renee T. Mo

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823864 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

    摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

    摘要翻译： 一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层，选择性地去除 仅第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。