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公开(公告)号：US20070196575A1
公开(公告)日：2007-08-23
申请号：US11359165
申请日：2006-02-21
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162 , Y10S977/742
摘要： Embodiments of the present invention provide methods for the fabrication of carbon nanotubes using composite metal films. A composite metal film is fabricated to provide uniform catalytic sites to facilitate the uniform growth of carbon nanotubes. Further embodiments provide embedded nanoparticles for carbon nanotube fabrication. Embodiments of the invention are capable of maintaining the integrity of the catalytic sites at temperatures used in carbon nanotube fabrication processes, 600 to 1100° C.
摘要翻译： 本发明的实施例提供了使用复合金属膜制造碳纳米管的方法。 制造复合金属膜以提供均匀的催化位点以促进碳纳米管的均匀生长。 另外的实施方案提供用于碳纳米管制造的嵌入式纳米颗粒。 本发明的实施方案能够在碳纳米管制造工艺中使用的温度下维持催化部位的完整性，其温度为600至1100℃
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公开(公告)号：US20060281306A1
公开(公告)日：2006-12-14
申请号：US11148614
申请日：2005-06-08
申请人： Florian Gstrein , Adrien Lavoie , Valery Dubin , Juan Dominguez
发明人： Florian Gstrein , Adrien Lavoie , Valery Dubin , Juan Dominguez
IPC分类号： H01L21/44
CPC分类号： H01L23/53276 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect on a semiconductor substrate comprises providing at least one carbon nanotube within a trench, etching at least one portion of the carbon nanotube to create an opening, conformally depositing a metal layer on the carbon nanotube through the opening, and forming a metallized contact at the opening that is substantially coupled to the carbon nanotube. The metal layer may be conformally deposited on the carbon nanotube using an atomic layer deposition process or an electroless plating process. Multiple metal layers may be deposited to substantially fill voids within the carbon nanotube. The electroless plating process may use a supercritical liquid as the medium for the plating solution. The wetting behavior of the carbon nanotube may be modified prior to the electroless plating process to increase the hydrophilicity of the carbon nanotube.
摘要翻译： 一种用于在半导体衬底上形成互连的方法包括在沟槽内提供至少一个碳纳米管，蚀刻碳纳米管的至少一部分以形成开口，通过开口在碳纳米管上共形沉积金属层，并形成 在开口处的金属化接触基本上与碳纳米管耦合。 可以使用原子层沉积工艺或无电镀工艺将金属层共形沉积在碳纳米管上。 可以沉积多个金属层以基本上填充碳纳米管内的空隙。 化学镀处理可以使用超临界液体作为电镀溶液的介质。 可以在化学镀处理之前改变碳纳米管的润湿性能，以增加碳纳米管的亲水性。
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公开(公告)号：US20070155158A1
公开(公告)日：2007-07-05
申请号：US11325774
申请日：2005-12-30
申请人： Florian Gstrein , Valery Dubin , Juan Dominguez , Adrien Lavoie
发明人： Florian Gstrein , Valery Dubin , Juan Dominguez , Adrien Lavoie
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76838 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/75 , H01L2924/00
摘要： A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.
摘要翻译： 一种包括在牺牲衬底上形成单层碳纳米管的互连的方法; 将所述互连件从所述牺牲衬底转移到电路衬底; 以及将所述互连件耦合到所述电路基板上的接触点。 一种方法，包括在第一接触点和第二接触点之间的电路基板上形成纳米管束，所述纳米管限定通过其的腔; 用导电材料填充纳米管束管腔长度的一部分; 以及将所述导电材料耦合到所述第二接触点。 一种包括计算设备的系统，包括微处理器，微处理器耦合到印刷电路板，微处理器包括具有多个电路器件的衬底，该电路器件具有通过包括碳纳米管束的互连结构与多个电路器件形成的电连接。
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4.发明申请Method and CMOS-based device to analyze molecules and nanomaterials based on the electrical readout of specific binding events on functionalized electrodes 审中-公开基于功能化电极上特异性结合事件的电气读出的方法和基于CMOS的器件来分析分子和纳米材料公开(公告)号：US20070292855A1
公开(公告)日：2007-12-20
申请号：US11207000
申请日：2005-08-19
申请人： Valery Dubin , Florian Gstrein , Jonathan Lueker
发明人： Valery Dubin , Florian Gstrein , Jonathan Lueker
CPC分类号： C12Q1/6816 , C12Q2565/607
摘要： A device having a functionalized electrode having a probe molecule, wherein the device has an ability to electrically detect a molecular binding event between the probe molecule and a target molecule by a polarization change of the functionalized electrode is disclosed. The device could also include an unfunctionalized electrode that does not have the probe molecule and the device could have an ability to electrically detect the molecular binding event between the probe molecule and the target molecule by a polarization change between the functionalized electrode and the unfuctionalized electrode.
摘要翻译： 具有具有探针分子的官能化电极的器件，其中该器件具有通过官能化电极的偏振变化电探测探针分子与靶分子之间的分子结合事件的能力。 该装置还可以包括不具有探针分子的未官能化电极，并且该装置可以具有通过功能化电极和未通电电极之间的偏振变化来电探测分子与靶分子之间的分子结合事件的能力。
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5.发明申请公开(公告)号：US20060275927A1
公开(公告)日：2006-12-07
申请号：US11144679
申请日：2005-06-06
申请人： Valery Dubin , Florian Gstrein , Gordon Holt , Brandon Barnett
发明人： Valery Dubin , Florian Gstrein , Gordon Holt , Brandon Barnett
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
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公开(公告)号：US20070248794A1
公开(公告)日：2007-10-25
申请号：US11408745
申请日：2006-04-21
申请人： Florian Gstrein , James Blackwell , Amlan Majumdar , Valery Dubin
发明人： Florian Gstrein , James Blackwell , Amlan Majumdar , Valery Dubin
CPC分类号： H01L23/53276 , B82Y10/00 , H01L23/49877 , H01L2924/0002 , Y10T428/24322 , H01L2924/00
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming an opening in a substrate, placing at least one multi-walled CNT within the opening, and forming a carbide layer on the at least one multi-walled CNT.
摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在基底中形成开口，将至少一个多壁CNT放置在开口内，以及在至少一个多壁CNT上形成碳化物层。
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公开(公告)号：US20060267051A1
公开(公告)日：2006-11-30
申请号：US11136585
申请日：2005-05-25
申请人： Florian Gstrein , Valery Dubin
发明人： Florian Gstrein , Valery Dubin
IPC分类号： H01L29/15
CPC分类号： G01N27/129
摘要： A metal oxide sensor is provided on a semiconductor substrate to provide on-chip sensing of gases. The sensor may include a metal layer that may have pores formed by lithography to be of a certain width. The top metal layer may be oxidized resulting in a narrowing of the pores. Another metal layer may be formed over the oxidized layer and electrical contacts may be formed on the metal layer. The contacts may be coupled to a monitoring system that receives electrical signals indicative of gases sensed by the metal oxide sensor.
摘要翻译： 金属氧化物传感器设置在半导体衬底上以提供对气体的片上感测。 传感器可以包括可以具有通过光刻形成的孔以具有一定宽度的金属层。 顶部金属层可能被氧化，导致孔变窄。 可以在氧化层之上形成另一金属层，并且可以在金属层上形成电接触。 触点可以耦合到监测系统，监测系统接收指示由金属氧化物传感器感测的气体的电信号。
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公开(公告)号：US07635503B2
公开(公告)日：2009-12-22
申请号：US11359165
申请日：2006-02-21
IPC分类号： C23C16/00
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162 , Y10S977/742
摘要： Embodiments of the present invention provide methods for the fabrication of carbon nanotubes using composite metal films. A composite metal film is fabricated to provide uniform catalytic sites to facilitate the uniform growth of carbon nanotubes. Further embodiments provide embedded nanoparticles for carbon nanotube fabrication. Embodiments of the invention are capable of maintaining the integrity of the catalytic sites at temperatures used in carbon nanotube fabrication processes, 600 to 1100° C.
摘要翻译： 本发明的实施例提供了使用复合金属膜制造碳纳米管的方法。 制造复合金属膜以提供均匀的催化位点以促进碳纳米管的均匀生长。 另外的实施方案提供用于碳纳米管制造的嵌入式纳米颗粒。 本发明的实施方案能够在碳纳米管制造工艺中使用的温度下维持催化部位的完整性，其温度为600至1100℃
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9.发明授权Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) 有权通过原子层沉积（ALD）和化学气相沉积（CVD）选择性地沉积金属膜公开(公告)号：US09583389B2
公开(公告)日：2017-02-28
申请号：US14960104
申请日：2015-12-04
IPC分类号： H01L21/768 , H01L21/285 , C23C16/04 , C23C16/18 , C23C16/455
CPC分类号： H01L21/76897 , C23C16/04 , C23C16/18 , C23C16/45525 , H01L21/28506 , H01L21/28562 , H01L21/76801 , H01L21/76816 , H01L21/76838 , H01L21/76849 , H01L21/76879
摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
摘要翻译： 描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。 在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。 该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。
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10.发明申请公开(公告)号：US20160086850A1
公开(公告)日：2016-03-24
申请号：US14960104
申请日：2015-12-04
IPC分类号： H01L21/768 , H01L21/285
CPC分类号： H01L21/76897 , C23C16/04 , C23C16/18 , C23C16/45525 , H01L21/28506 , H01L21/28562 , H01L21/76801 , H01L21/76816 , H01L21/76838 , H01L21/76849 , H01L21/76879
摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
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