公开(公告)号：US08791577B2

公开(公告)日：2014-07-29

申请号：US13617952

申请日：2012-09-14

申请人： Juhan Kim ,  Jongwook Kye

发明人： Juhan Kim ,  Jongwook Kye

IPC分类号： H01L23/48 ,  H01L29/66 ,  H01L23/52 ,  H01L21/4763

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure; providing, via a second patterning process of the metal layer, a second structure that is different from the first structure and that is a second one of the word line structure, the ground line structure, the power line structure, and the bit line structure; and providing, via a third patterning process of the metal layer, a third structure that is different from the first structure and the second structure, and that is a third one of the word line structure, the ground line structure line, the power line structure, and the bit line structure.

摘要翻译： 公开了一种用于提供具有三层图案化金属层结构的位单元的方法。 实施例包括：通过金属层的第一图案化工艺提供作为字线结构，接地线结构，电力线结构和位线结构中的第一个的第一结构; 通过所述金属层的第二图案化处理提供与所述第一结构不同的第二结构，并且所述第二结构是所述字线结构，所述接地线结构，所述电力线结构和所述位线结构中的第二结构。 并且经由所述金属层的第三图案化处理提供与所述第一结构和所述第二结构不同的第三结构，并且所述第三结构是所述字线结构，所述接地线结构线，所述电力线结构 ，和位线结构。

公开(公告)号：US20140077384A1

公开(公告)日：2014-03-20

申请号：US13617952

申请日：2012-09-14

申请人： Juhan Kim ,  Jongwook Kye

发明人： Juhan Kim ,  Jongwook Kye

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure; providing, via a second patterning process of the metal layer, a second structure that is different from the first structure and that is a second one of the word line structure, the ground line structure, the power line structure, and the bit line structure; and providing, via a third patterning process of the metal layer, a third structure that is different from the first structure and the second structure, and that is a third one of the word line structure, the ground line structure line, the power line structure, and the bit line structure.

摘要翻译： 公开了一种用于提供具有三层图案化金属层结构的位单元的方法。 实施例包括：通过金属层的第一图案化工艺提供作为字线结构，接地线结构，电力线结构和位线结构中的第一个的第一结构; 通过所述金属层的第二图案化处理提供与所述第一结构不同的第二结构，并且所述第二结构是所述字线结构，所述接地线结构，所述电力线结构和所述位线结构中的第二结构。 并且经由所述金属层的第三图案化处理提供与所述第一结构和所述第二结构不同的第三结构，并且所述第三结构是所述字线结构，所述接地线结构线，所述电力线结构 ，和位线结构。

公开(公告)号：US08889561B2

公开(公告)日：2014-11-18

申请号：US13709541

申请日：2012-12-10

申请人： Youngtag Woo ,  Jongwook Kye ,  Dinesh Somasekhar

发明人： Youngtag Woo ,  Jongwook Kye ,  Dinesh Somasekhar

IPC分类号： H01L21/308 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/088

CPC分类号： H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

摘要： Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

摘要翻译： 公开了能够产生具有可变翅片间距小于40nm的翅片的方法，并且所得到的装置被公开。 实施例包括：在基板上形成硬掩模; 在硬掩模上提供第一和第二心轴; 在每个第一和第二心轴的每一侧上提供第一间隔件; 去除第一和第二心轴; 在移除所述第一和第二心轴之后，在每个所述第一间隔件的每一侧上提供第二间隔件; 并移除第一间隔物。

公开(公告)号：US20140159164A1

公开(公告)日：2014-06-12

申请号：US13709541

申请日：2012-12-10

申请人： Youngtag WOO ,  Jongwook Kye ,  Dinesh Somasekhar

发明人： Youngtag WOO ,  Jongwook Kye ,  Dinesh Somasekhar

IPC分类号： H01L21/308 ,  H01L27/088

CPC分类号： H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

摘要： Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

公开(公告)号：US20140068543A1

公开(公告)日：2014-03-06

申请号：US13603304

申请日：2012-09-04

申请人： Lei Yuan ,  Jongwook Kye

发明人： Lei Yuan ,  Jongwook Kye

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part, a presentation in the user interface of a cell placement of the IC that includes a filler cell; and designating a portion of the filler cell as a routing zone, the routing zone being configured such that routes placed in the routing zone are decomposable with other routes placed outside the filler cell.

摘要翻译： 公开了一种使用DPT实现电路设计中的点动功能的方法，而不需要难以实现诸如针迹感知路由工具的工具。 实施例包括：显示用于生成具有用于单层的多个掩模的IC的用户界面; 至少部分地使得包括填充单元的IC的单元放置的用户界面中的呈现; 并且将所述填充单元的一部分指定为路由区域，所述路由区域被配置为使得放置在所述路由区域中的路由可以与放置在所述填充单元之外的其他路由分解。

公开(公告)号：US20130298089A1

公开(公告)日：2013-11-07

申请号：US13465909

申请日：2012-05-07

申请人： Lei Yuan ,  Hidekazu Yoshida ,  Youngtag Woo ,  Jongwook Kye

发明人： Lei Yuan ,  Hidekazu Yoshida ,  Youngtag Woo ,  Jongwook Kye

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： A method for increasing the robustness of a double patterning router used in the manufacture of integrated circuit devices that includes providing a set of original color rules defining an original color rule space, providing a set of integrated circuit designs defining a design space, providing a router processing engine, perturbing the original color rules to define a perturbed color rule space, applying the perturbed color rule space and the design space to the router processing engine to expose double pattern routing odd cycle decomposition errors, and feeding back the exposed decomposition errors to enhance router processing engine development by reconfiguring the router processing engine in accordance with the exposed decomposition errors.

摘要翻译： 一种用于增加用于制造集成电路器件的双重图案化路由器的鲁棒性的方法，其包括提供定义原始颜色规则空间的一组原始颜色规则，提供定义设计空间的一组集成电路设计，提供路由器 处理引擎，扰乱原始颜色规则以定义扰动的颜色规则空间，将扰动的颜色规则空间和设计空间应用于路由器处理引擎以暴露双模式路由奇数周期分解错误，并反馈暴露的分解错误以增强 通过根据暴露的分解错误重新配置路由器处理引擎来开发路由器处理引擎。

公开(公告)号：US20130295756A1

公开(公告)日：2013-11-07

申请号：US13465633

申请日：2012-05-07

申请人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

发明人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

IPC分类号： H01L21/28 ,  H01L21/283

CPC分类号： H01L21/823475 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

摘要翻译： 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。

公开(公告)号：US20130146982A1

公开(公告)日：2013-06-13

申请号：US13324699

申请日：2011-12-13

申请人： Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L27/088

CPC分类号： H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 CA层电连接到第一晶体管的源极或漏极中的至少一个。 CB层电连接到晶体管和CA层的至少一个栅极。

公开(公告)号：US08367430B2

公开(公告)日：2013-02-05

申请号：US12575068

申请日：2009-10-07

申请人： Yuansheng Ma ,  Harry J. Levinson ,  Jongwook Kye

发明人： Yuansheng Ma ,  Harry J. Levinson ,  Jongwook Kye

IPC分类号： H01L21/66

CPC分类号： G06F17/5081 ,  G06F2217/10

摘要： Shapes and orientations of contacts or other closed contours on an integrated circuit are characterized by calculating Elliptic Fourier descriptors. The descriptors are then used for generating design rules for the integrated circuit and for assessing process capability for the manufacturing of the integrated circuit. Monte Carlo simulation can be performed in conjunction with the elliptic Fourier descriptors.

摘要翻译： 集成电路上触点或其他封闭轮廓的形状和方向的特征在于计算椭圆傅立叶描述符。 然后将描述符用于生成集成电路的设计规则并用于评估集成电路制造的处理能力。 可以与椭圆傅立叶描述符一起执行蒙特卡罗模拟。

公开(公告)号：US08324106B2

公开(公告)日：2012-12-04

申请号：US13079647

申请日：2011-04-04

申请人： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

发明人： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC分类号： H01L21/311

CPC分类号： G03F1/38 ,  G03F1/70

摘要： Methods are provided for designing a photolithographic mask and for fabricating a semiconductor IC using such a mask. In accordance with one embodiment a method for fabricating a semiconductor IC includes determining a design target for a region within the IC. An initial mask geometry is determined for the region having a mask opening and a mask bias relative to the design target. A sub-resolution edge ring having a predetermined, fixed spacing to an edge of the mask opening is inserted into the mask geometry and a lithographic mask is generated. A material layer is applied overlying a semiconductor substrate upon which the IC is to be fabricated and a layer of photoresist is applied overlying the material layer. The layer of photoresist is exposed through the lithographic mask and is developed. A process step is then performed on the material layer using the layer of photoresist as a mask.

摘要翻译： 提供了用于设计光刻掩模和使用这种掩模制造半导体IC的方法。 根据一个实施例，制造半导体IC的方法包括确定IC内的区域的设计目标。 对于具有掩模开口的区域和相对于设计目标的掩模偏置确定初始掩模几何形状。 具有与掩模开口的边缘的预定的固定间隔的子分辨率边缘环被插入到掩模几何形状中，并且产生光刻掩模。 应用覆盖在其上将要制造IC的半导体衬底上的材料层，并且覆盖在该材料层上的光致抗蚀剂层。 光致抗蚀剂层通过光刻掩模曝光并显影。 然后使用光致抗蚀剂层作为掩模在材料层上进行处理步骤。