公开(公告)号：US07162590B2

公开(公告)日：2007-01-09

申请号：US10788315

申请日：2004-03-01

申请人： Julie-Anne Francoise Marie Pruvost ,  Norbert Bernard Eugene Lataille ,  Stuart David Biles

发明人： Julie-Anne Francoise Marie Pruvost ,  Norbert Bernard Eugene Lataille ,  Stuart David Biles

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0831

摘要： Within a coherent multi-processing system multiple processor cores 4, 6 are coupled via respective memory buses to a memory access control unit 16. The memory buses are formed of a uni-processing portion containing signals specifying a memory access request in accordance with a uni-processing protocol. This uni-processing bus is augmented by a multi-processing bus containing signals giving additional information concerning memory access requests which may be used by the memory access control unit to service those requests and manage coherency within the system.

摘要翻译： 在相干多处理系统中，多个处理器核心4,6通过相应的存储器总线耦合到存储器访问控制单元16。 存储器总线由根据单处理协议的包含指定存储器访问请求的信号的单处理部分形成。 这种单处理总线由包含信号的多处理总线增加，该信号提供关于存储器访问请求的附加信息，存储器访问控制单元可以由存储器访问控制单元使用来为这些请求提供服务并且管理系统内的一致性。

公开(公告)号：US20080109639A1

公开(公告)日：2008-05-08

申请号：US11592337

申请日：2006-11-03

申请人： Elodie Charra ,  Frederic Claude Marie Piry ,  Richard Roy Grisenthwaite ,  Melanie Emanuelle Lucie Vincent ,  Norbert Bernard Eugene Lataille ,  Jocelyn Francois Orion Jaubert ,  Stuart David Biles

发明人： Elodie Charra ,  Frederic Claude Marie Piry ,  Richard Roy Grisenthwaite ,  Melanie Emanuelle Lucie Vincent ,  Norbert Bernard Eugene Lataille ,  Jocelyn Francois Orion Jaubert ,  Stuart David Biles

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F15/8007 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/3897 ,  G06F12/0837

摘要： A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster. Such a mechanism provides a particularly efficient technique to cause each of the processing units in the cluster to perform an identical operation which can be useful in a variety of situations, for example in an SMP system where coherency of data is required and accordingly maintenance operations need to be performed periodically within each processing unit to ensure such coherency.

摘要翻译： 提供了一种用于处理具有多个处理单元的数据处理装置内的指令执行的数据处理装置和方法。 每个处理单元可操作以执行指令序列，以便执行相关联的操作，并且处理单元的至少一个子集形成一个簇。 提供了指令转发逻辑，对于由集群中的至少一个处理单元执行的至少一个指令，导致该指令由集群中的每个其他处理单元执行，例如通过使该指令被插入 由群集中的每个其他处理单元执行的指令序列。 这样的机制提供了一种特别有效的技术，以使群集中的每个处理单元执行相同的操作，其可以在各种情况下有用，例如在需要数据的一致性并因此需要维护操作的SMP系统中 以在每个处理单元内周期性地执行以确保这样的一致性。

公开(公告)号：US09513959B2

公开(公告)日：2016-12-06

申请号：US12149003

申请日：2008-04-24

申请人： Stuart David Biles ,  Geoffrey Blake ,  Trevor Nigel Mudge

发明人： Stuart David Biles ,  Geoffrey Blake ,  Trevor Nigel Mudge

IPC分类号： G06F9/46 ,  G06F9/52 ,  G06F9/48

CPC分类号： G06F9/466 ,  G06F9/467 ,  G06F9/4881 ,  G06F9/528

摘要： A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

摘要翻译： 在具有相关性控制和硬件事务存储器控制电路22的多处理器4,6,8,10系统内提供硬件事务存储器12,14,16,18,20，其用于至少部分地根据处理事务的调度来管理 在冲突数据26,28,30之间。冲突数据表征处理事务之前先前遇到的冲突。 执行调度，使得如果冲突数据指示已经运行的处理事务中的一个先前与候选处理事务冲突，则候选处理事务将不被调度。

公开(公告)号：US08200902B2

公开(公告)日：2012-06-12

申请号：US12801484

申请日：2010-06-10

申请人： Nigel Charles Paver ,  Stuart David Biles ,  Dam Sunwoo ,  Prakash Shyamlal Ramrakhyani

发明人： Nigel Charles Paver ,  Stuart David Biles ,  Dam Sunwoo ,  Prakash Shyamlal Ramrakhyani

IPC分类号： G06F12/00

CPC分类号： G06F12/0895 ,  G06F12/121 ,  Y02D10/13

摘要： A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilization, thereby giving rise to both performance improvements and power consumption reductions.

摘要翻译： 提供了一种缓存设备，用于在数据处理设备中用于存储由相关联的主设备访问的数据值。 每个数据值在存储器设备中具有相关联的存储器位置，并且存储器设备被布置为存储器位置的多个块，每个块必须在存储在该块中的任何数据值可被访问之前被激活。 高速缓存设备包括常规访问检测电路，用于检测对其相关联的存储器位置遵循规则模式的数据值的访问序列的发生。 在检测到常规访问检测电路的这种访问序列的发生时，高速缓存使用的用于确定存储数据值的所选高速缓存行的分配策略被改变，目的是增加当 由缓存输出的被驱逐的数据值随后被写入存储器件，相关联的存储器位置驻留在已经激活的存储器位置块中。 因此，通过检测常规访问模式，并且在检测到这种模式时改变分配策略，这使得能够在存储器件内重新使用已激活的块，从而显着提高存储器利用率，从而产生性能改善和功耗降低。

公开(公告)号：US08195886B2

公开(公告)日：2012-06-05

申请号：US11723189

申请日：2007-03-16

申请人： Emre Özer ,  Stuart David Biles

发明人： Emre Özer ,  Stuart David Biles

IPC分类号： G06F12/12

CPC分类号： G06F12/126

摘要： A data processing apparatus and method are provided for implementing a replacement scheme for entries of a storage unit. The data processing apparatus has processing circuitry for executing multiple program threads including at least one high priority program thread and at least one lower priority program thread. A storage unit is then shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. A record is maintained identifying for each entry whether the information stored in that entry is associated with a high priority program thread or a lower priority program thread. Replacement circuitry is then responsive to a predetermined event in order to select a victim entry whose stored information is to be replaced. To achieve this, the replacement circuitry performs a candidate generation operation to identify a plurality of randomly selected candidate entries, and then references the record in order to preferentially select as the victim entry a candidate entry whose stored information is associated with a lower priority program thread. This improves the performance of the high priority program thread(s) by preferentially evicting from the storage unit entries associated with lower priority program threads.

摘要翻译： 提供了一种数据处理装置和方法，用于实现用于存储单元的条目的替换方案。 数据处理装置具有用于执行包括至少一个高优先级程序线程和至少一个较低优先级程序线程的多个程序线程的处理电路。 然后，存储单元在多个程序线程之间共享，并且具有用于存储用于在执行程序线程时由处理电路参考的信息的多个条目。 维护记录以识别每个条目，存储在该条目中的信息是否与高优先级程序线程或较低优先级的程序线程相关联。 然后，替换电路响应于预定事件，以便选择其存储的信息将被替换的受害者条目。 为了实现这一点，替换电路执行候选生成操作以识别多个随机选择的候选条目，然后引用该记录，以优先选择其存储的信息与较低优先级的程序线程相关联的候选条目作为受害者条目 。 这通过优先从与优先级较低的程序线程相关联的存储单元条目中逐出来来提高高优先级程序线程的性能。

公开(公告)号：US07937535B2

公开(公告)日：2011-05-03

申请号：US11709279

申请日：2007-02-22

申请人： Emre Özer ,  Stuart David Biles ,  Simon Andrew Ford

发明人： Emre Özer ,  Stuart David Biles ,  Simon Andrew Ford

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0822 ,  Y02D10/13

摘要： Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.

摘要翻译： 多个处理单元中的每一个具有高速缓存，并且每个高速缓存具有包含段过滤数据的指示电路。 指示电路响应来自相关联的处理单元的访问请求指定的地址以引用段过滤数据，以指示数据是否被明确地不存储或潜在地存储在该段中。 高速缓存一致性电路确保每个处理单元访问的数据是最新的，并且具有其内容源自已经提供的段过滤数据的窥探指示电路。 对于某些访问请求，高速缓存一致性电路发起一致性操作，在此期间，窥探指示电路确定是否有任何缓存需要窥探操作。 对于每个缓存，高速缓存一致性电路向该缓存发出一个通知，用于标识要执行的侦听操作。

公开(公告)号：US07886098B2

公开(公告)日：2011-02-08

申请号：US11898640

申请日：2007-09-13

申请人： Daniel Kershaw ,  Stuart David Biles

发明人： Daniel Kershaw ,  Stuart David Biles

IPC分类号： G06F13/00 ,  G06F13/28 ,  H04L29/06 ,  H02H9/00

CPC分类号： G06F12/1416 ,  G06F12/1491

摘要： A data processing apparatus and method for generating access requests is provided. A bus master is provided which can operate either in a secure domain or a non-secure domain of the data processing apparatus, according to a signal received from external to the bus master. The signal is generated to be fixed during normal operation of the bus master. Control logic is provided which, when the bus master device is operating in a secure domain, is operable to generate a domain specifying signal associated with an access request generated by the bus master core indicating either secure or non-secure access, in dependence on either a default memory map or securely defined memory region descriptors. Thus, the bus master operating in a secure domain can generate both secure and non-secure accesses, without itself being able to switch between secure and non-secure operation.

摘要翻译： 提供了一种用于产生访问请求的数据处理装置和方法。 根据从总线主机外部接收的信号，提供可以在数据处理装置的安全域或非安全域中操作的总线主机。 在总线主机的正常工作期间，生成固定信号。 提供控制逻辑，当总线主设备在安全域中操作时，可以根据总线主机核心生成的指示安全或非安全访问的访问请求产生一个域指定信号， 默认内存映射或安全定义的内存区域描述符。 因此，在安全域中操作的总线主机可以生成安全和非安全访问，而无需在安全和非安全操作之间进行切换。

公开(公告)号：US20090319707A1

公开(公告)日：2009-12-24

申请号：US12213470

申请日：2008-06-19

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F13/40

CPC分类号： G06F13/4221

摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

公开(公告)号：US20090216958A1

公开(公告)日：2009-08-27

申请号：US12071505

申请日：2008-02-21

申请人： Stuart David Biles ,  Nigel Charles Paver ,  Chander Sudanthi

发明人： Stuart David Biles ,  Nigel Charles Paver ,  Chander Sudanthi

IPC分类号： G06F13/40

CPC分类号： G06F13/1668 ,  G06F2213/0038

摘要： A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor 4 and the hardware accelerator 6 share a memory system 8. A first communication channel 12 between the processor 4 and the hardware accelerator 6 communicates at least control signals therebetween. A second communication channel 14 coupling the hardware accelerator 6 and the memory system 8 allows the hardware accelerator 6 to perform its own data access operations upon the memory system 8.

摘要翻译： 集成电路2形式的数据处理系统包括通用可编程处理器4和硬件加速器6.共享存储器管理单元10代表处理器核心4和硬件加速器6两者提供存储器管理操作。 处理器4和硬件加速器6共享存储器系统8.处理器4和硬件加速器6之间的第一通信信道12至少在其间通信控制信号。 耦合硬件加速器6和存储器系统8的第二通信通道14允许硬件加速器6在存储器系统8上执行其自己的数据访问操作。

公开(公告)号：US20090150620A1

公开(公告)日：2009-06-11

申请号：US12000005

申请日：2007-12-06

申请人： Nigel Charles Paver ,  Stuart David Biles

发明人： Nigel Charles Paver ,  Stuart David Biles

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F9/3879 ,  G06F12/0815 ,  G06F12/1027

摘要： A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

摘要翻译： 数据处理装置2包括耦合到硬件加速器12的可编程通用处理器10.存储器系统14,6,8由处理器10和硬件加速器12共享。存储器系统监视电路16响应于一个或多个 由处理器10在存储器系统14,6,8上执行的预定操作，以产生对硬件加速器12的触发，以使其停止其处理操作，并清除作为硬件加速器的寄存器20内的临时变量所保持的任何数据值。 存储器系统14,6,8。