公开(公告)号：US08436331B2

公开(公告)日：2013-05-07

申请号：US12844374

申请日：2010-07-27

申请人： Yoko Iwakaji ,  Jun Hirota ,  Kyoichi Suguro ,  Moto Yabuki

发明人： Yoko Iwakaji ,  Jun Hirota ,  Kyoichi Suguro ,  Moto Yabuki

IPC分类号： H01L21/02

CPC分类号： H01L27/1021 ,  G11C13/0007 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675

摘要： According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.

摘要翻译： 根据一个实施例，公开了一种用于制造存储器件的方法。 该方法包括形成硅二极管。 至少硅二极管的上部由含有硅并掺杂杂质的半导体材料制成。 该方法包括在硅二极管上形成由金属制成的金属层。 该方法包括在金属层上形成由金属的氮化物制成的金属氮化物层。 该方法包括形成电阻变化膜。 此外，该方法包括通过热处理使金属层与硅二极管和金属氮化物层反应，以形成含有金属，硅和氮的电极膜。

公开(公告)号：US08309958B2

公开(公告)日：2012-11-13

申请号：US12872284

申请日：2010-08-31

申请人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

发明人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

IPC分类号： H01L29/06 ,  H01L29/12 ,  H01L45/00

CPC分类号： H01L27/1021 ,  H01L27/101

摘要： According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.

摘要翻译： 根据一个实施例，半导体存储器件包括字线互连层，位线互连层和柱。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向交叉的第二方向延伸的多个位线。 支柱布置在每个字线和每个位线之间。 支柱包括硅二极管和可变电阻膜，并且硅二极管包括p型部分和n型部分。 字线互连层和位线互连层交替堆叠，并且在p型部分和n型部分变得更接近的方向上对硅二极管施加压缩力。

公开(公告)号：US20120091414A1

公开(公告)日：2012-04-19

申请号：US13052143

申请日：2011-03-21

申请人： Yoko IWAKAJI ,  Jun Hirota ,  Moto Yabuki ,  Wakana Kai ,  Hirokazu Ishida ,  Ichiro Mizushima

发明人： Yoko IWAKAJI ,  Jun Hirota ,  Moto Yabuki ,  Wakana Kai ,  Hirokazu Ishida ,  Ichiro Mizushima

IPC分类号： H01L47/00 ,  H01L21/20 ,  H01L29/04

CPC分类号： H01L29/045 ,  H01L21/02425 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L29/685 ,  H01L29/868 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675

摘要： According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.

摘要翻译： 根据一个实施例，半导体器件包括多个硅膜。 多个硅膜设置在一个平面上，由含有杂质的多晶硅制成。 每个硅膜的晶体取向为（311）取向。

公开(公告)号：US08664631B2

公开(公告)日：2014-03-04

申请号：US13236713

申请日：2011-09-20

申请人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

发明人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.

摘要翻译： 根据一个实施例，非易失性存储器件包括字线互连层，位线互连层，柱和电荷承载部件。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向相交的第二方向延伸的多个位线。 支柱设置在每个字线和每个位线之间。 电荷承载部件包含负的固定电荷，并且设置在支柱的侧面上。 支柱包括二极管膜，该二极管膜设置有层叠在二极管膜上的p型层和n型层以及可变电阻膜。 电荷承载部件配置在p型层的侧面，不配置在n型层的侧面。

公开(公告)号：US20110193049A1

公开(公告)日：2011-08-11

申请号：US12844374

申请日：2010-07-27

申请人： Yoko IWAKAJI ,  Jun Hirota ,  Kyoichi Suguro ,  Moto Yabuki

发明人： Yoko IWAKAJI ,  Jun Hirota ,  Kyoichi Suguro ,  Moto Yabuki

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L27/1021 ,  G11C13/0007 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675

摘要： According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.

摘要翻译： 根据一个实施例，公开了一种用于制造存储器件的方法。 该方法包括形成硅二极管。 硅二极管的至少上部由含有硅并掺杂杂质的半导体材料制成。 该方法包括在硅二极管上形成由金属制成的金属层。 该方法包括在金属层上形成由金属的氮化物制成的金属氮化物层。 该方法包括形成电阻变化膜。 此外，该方法包括通过热处理使金属层与硅二极管和金属氮化物层反应，以形成含有金属，硅和氮的电极膜。

公开(公告)号：US08558354B2

公开(公告)日：2013-10-15

申请号：US13052143

申请日：2011-03-21

申请人： Yoko Iwakaji ,  Jun Hirota ,  Moto Yabuki ,  Wakana Kai ,  Hirokazu Ishida ,  Ichiro Mizushima

发明人： Yoko Iwakaji ,  Jun Hirota ,  Moto Yabuki ,  Wakana Kai ,  Hirokazu Ishida ,  Ichiro Mizushima

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/02425 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L29/685 ,  H01L29/868 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675

摘要： According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.

摘要翻译： 根据一个实施例，半导体器件包括多个硅膜。 多个硅膜设置在一个平面上，由含有杂质的多晶硅制成。 每个硅膜的晶体取向为（311）取向。

公开(公告)号：US20120235107A1

公开(公告)日：2012-09-20

申请号：US13236713

申请日：2011-09-20

申请人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

发明人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.

摘要翻译： 根据一个实施例，非易失性存储器件包括字线互连层，位线互连层，柱和电荷承载部件。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向相交的第二方向延伸的多个位线。 支柱设置在每个字线和每个位线之间。 电荷承载部件包含负的固定电荷，并且设置在支柱的侧面上。 支柱包括二极管膜，该二极管膜设置有层叠在二极管膜上的p型层和n型层以及可变电阻膜。 电荷承载部件配置在p型层的侧面，不配置在n型层的侧面。

公开(公告)号：US20110227025A1

公开(公告)日：2011-09-22

申请号：US12872284

申请日：2010-08-31

申请人： Jun HIROTA ,  Yoko Iwakaji ,  Moto Yabuki

发明人： Jun HIROTA ,  Yoko Iwakaji ,  Moto Yabuki

IPC分类号： H01L45/00 ,  H01L29/868 ,  H01L21/77

CPC分类号： H01L27/1021 ,  H01L27/101

摘要： According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.

摘要翻译： 根据一个实施例，半导体存储器件包括字线互连层，位线互连层和柱。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向交叉的第二方向延伸的多个位线。 支柱布置在每个字线和每个位线之间。 支柱包括硅二极管和可变电阻膜，并且硅二极管包括p型部分和n型部分。 字线互连层和位线互连层交替堆叠，并且在p型部分和n型部分变得更接近的方向上对硅二极管施加压缩力。

公开(公告)号：US20130077461A1

公开(公告)日：2013-03-28

申请号：US13423755

申请日：2012-03-19

申请人： Akihiro Koga ,  Yasushi Tomizawa ,  Hideo Shinomiya ,  Moto Yabuki ,  Jun Hirota ,  Yoshihisa Iwata ,  Masayuki Ichige ,  Kikuko Sugimae ,  Junya Matsunami

发明人： Akihiro Koga ,  Yasushi Tomizawa ,  Hideo Shinomiya ,  Moto Yabuki ,  Jun Hirota ,  Yoshihisa Iwata ,  Masayuki Ichige ,  Kikuko Sugimae ,  Junya Matsunami

IPC分类号： G11B9/00

CPC分类号： G11B9/02 ,  G11B9/1418 ,  G11B9/1436

摘要： A storage device includes a recording medium, a probe, a substrate, and a processing unit. The recording medium stores a signal. The probe reads or writes the signal to/from the recording medium. The substrate is provided with the probe via a conductive anchor interposed therebetween and a first connection terminal connected to the probe. The processing unit is provided on the substrate and has a second connection terminal. The second connection terminal is connected to the first connection terminal.

摘要翻译： 存储装置包括记录介质，探针，基板和处理单元。 记录介质存储信号。 探头将信号读取或写入记录介质。 基板经由插入其间的导电锚固体和连接到探针的第一连接端子设置有探针。 处理单元设置在基板上，并具有第二连接端子。 第二连接端子连接到第一连接端子。

公开(公告)号：US20110147822A1

公开(公告)日：2011-06-23

申请号：US12929894

申请日：2011-02-23

申请人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

发明人： Kenji Aoyama ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/764 ,  H01L29/40114 ,  H01L29/66825

摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.