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    Liquid crystal display device and method of driving a liquid crystal display device
    1.
    发明授权
    Liquid crystal display device and method of driving a liquid crystal display device 失效
    液晶显示装置及驱动液晶显示装置的方法

    公开(公告)号：US07268756B2

    公开(公告)日：2007-09-11

    申请号：US10650930

    申请日：2003-08-29

    申请人： Jun Koyama ,  Yutaka Shionoiri ,  Hiroyuki Miyake ,  Yasuhiro Hirayama ,  Buyeol Lee

    发明人： Jun Koyama ,  Yutaka Shionoiri ,  Hiroyuki Miyake ,  Yasuhiro Hirayama ,  Buyeol Lee

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0297 ,  G09G2320/0233

    摘要： A liquid crystal display device having analog buffer circuits, which is reduced in luminance fluctuation is provided. A source signal line driver circuit has a plurality of analog buffer circuits, the plurality of source signal lines and the plurality of analog buffer circuits constitute a circuit group, and source signal lines connected to the analog buffer circuits are switched their connections to different analog buffer circuits each time a new period is started. Therefore, output fluctuation among the analog buffer circuits is averaged and a uniform image can be displayed on the screen.

    摘要翻译： 提供一种具有减少亮度波动的模拟缓冲电路的液晶显示装置。 源信号线驱动电路具有多个模拟缓冲电路，多个源极信号线和多个模拟缓冲电路构成电路组，连接到模拟缓冲电路的源极信号线将其连接切换到不同的模拟缓冲器 每次启动一个新的时期的电路。 因此，模拟缓冲电路之间的输出波动被平均化并且可以在屏幕上显示均匀的图像。

    Circuit having source follower and semiconductor device having the circuit
    4.
    发明授权
    Circuit having source follower and semiconductor device having the circuit 失效

    公开(公告)号：US07081774B2

    公开(公告)日：2006-07-25

    申请号：US10893936

    申请日：2004-07-20

    申请人： Hiroyuki Miyake ,  Yutaka Shionoiri

    发明人： Hiroyuki Miyake ,  Yutaka Shionoiri

    IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/082 ,  G11C11/14 ,  G11C11/44

    CPC分类号： G09G3/20 ,  G09G2310/0275 ,  H03F1/301 ,  H03F3/505

    摘要： When a potential of a power supply line varies according to a flowing current, the gate-source voltage Vgs of a transistor also varies, leading to variations in the constant current between each source follower. In order to solve this problem, a potential Vb of the gate terminal of a transistor as a constant current source is changed in the same manner as a power supply line Vss which is connected to the source terminal of the transistor. Therefore, variations in the constant current are suppressed and variations in the output of the source followers are thus suppressed. In addition, by connecting the circuit having source followers to the output side of a signal line driver circuit, it can be prevented that luminance unevenness of a striped pattern is recognized in a display portion of a semiconductor device.

    Pulse output circuit, shift register and electronic equipment
    5.
    发明申请
    Pulse output circuit, shift register and electronic equipment 有权
    脉冲输出电路，移位寄存器和电子设备

    公开(公告)号：US20050062515A1

    公开(公告)日：2005-03-24

    申请号：US10958568

    申请日：2004-10-06

    申请人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    发明人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    IPC分类号： G02F1/1345 ,  G02F1/133 ,  G02F1/1368 ,  G06F1/04 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H01L51/50 ,  H03K3/013 ,  H03K3/353 ,  H03K17/00 ,  H03K17/693 ,  H03K19/0175 ,  H03L5/00 ,  H05B33/14

    CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

    摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

    摘要翻译： 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，后级的输出被输入到TFT103，使TFT103导通，同时电位 的TFT102和106的节点α的下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。

    Memory device and semiconductor device
    7.
    发明授权
    Memory device and semiconductor device 有权
    存储器件和半导体器件

    公开(公告)号：US09472559B2

    公开(公告)日：2016-10-18

    申请号：US12976340

    申请日：2010-12-22

    申请人： Yutaka Shionoiri ,  Hiroyuki Miyake ,  Kiyoshi Kato

    发明人： Yutaka Shionoiri ,  Hiroyuki Miyake ,  Kiyoshi Kato

    IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L27/115 ,  H01L27/12 ,  H01L27/13 ,  G11C16/04

    CPC分类号： H01L27/1052 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78648 ,  H01L29/7869

    摘要： It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

    摘要翻译： 本发明的目的是提供一种能够抑制功耗的存储器件和包括存储器件的半导体器件。 作为用作保持蓄积在用作存储元件的晶体管中的电荷的开关元件，为存储器件中的每个存储单元提供包括氧化物半导体膜作为有源层的晶体管。 用作存储元件的晶体管具有第一栅电极，第二栅电极，位于第一栅电极和第二栅电极之间的半导体膜，位于第一栅电极和半导体膜之间的第一绝缘膜， 位于第二栅电极和半导体膜之间的第二绝缘膜，以及与半导体膜接触的源电极和漏电极。

    Pulse Output Circuit, Shift Register and Electronic Equipment
    10.
    发明申请
    Pulse Output Circuit, Shift Register and Electronic Equipment 审中-公开
    脉冲输出电路，移位寄存器和电子设备

    公开(公告)号：US20060280279A1

    公开(公告)日：2006-12-14

    申请号：US11467022

    申请日：2006-08-24

    申请人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    发明人： Shou Nagao ,  Yoshifumi Tanada ,  Yutaka Shionoiri ,  Hiroyuki Miyake

    IPC分类号： G11C19/00

    CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0275 ,  G11C19/00

    摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

    摘要翻译： 一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。 一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。 当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。 因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。 另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为 高于（VDD + VthN）。 因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。 然后，随后阶段的输出被输入到TFT 103以使TFT 103导通，同时TFT 102和106的节点α的电位下降以使TFT 105关闭。 结果，输出节点的电位变为低电平。