公开(公告)号：US20130346643A1

公开(公告)日：2013-12-26

申请号：US14002945

申请日：2012-02-23

申请人： Jun Suzuki ,  Masahiko Takahashi ,  Youichi Hidaka ,  Teruyuki Baba ,  Takashi Yoshikawa

发明人： Jun Suzuki ,  Masahiko Takahashi ,  Youichi Hidaka ,  Teruyuki Baba ,  Takashi Yoshikawa

IPC分类号： G06F13/16

CPC分类号： G06F13/16 ,  G06F13/102 ,  G06F13/28 ,  G06F2213/0026

摘要： A CPU 80 controls data transfer from a first device to a second device in a kernel mode. A main memory 90 stores data to be transferred from the first device to the second device. The CPU 80 has: a first device control means 81 which controls the first device; a second device control means which controls the second device; and a data transfer control means 83 which makes a read instruction which instructs the first device control means 81 to store data read from the first device in the main memory 3, and makes a write instruction which instructs the second device control means 82 to write the data stored in the main memory 3 in the second device.

摘要翻译： CPU 80以内核模式控制从第一设备到第二设备的数据传输。 主存储器90存储要从第一设备传送到第二设备的数据。 CPU80具有：控制第一装置的第一装置控制装置81; 控制第二装置的第二装置控制装置; 以及数据传送控制装置83，其使得指令第一装置控制装置81将从第一装置读取的数据存储在主存储器3中的读取指令，并且进行指示第二装置控制装置82写入的写指令 存储在第二装置中的主存储器3中的数据。

公开(公告)号：US09280498B2

公开(公告)日：2016-03-08

申请号：US14002945

申请日：2012-02-23

申请人： Jun Suzuki ,  Masahiko Takahashi ,  Youichi Hidaka ,  Teruyuki Baba ,  Takashi Yoshikawa

发明人： Jun Suzuki ,  Masahiko Takahashi ,  Youichi Hidaka ,  Teruyuki Baba ,  Takashi Yoshikawa

IPC分类号： G06F13/28 ,  G06F13/16 ,  G06F13/10

CPC分类号： G06F13/16 ,  G06F13/102 ,  G06F13/28 ,  G06F2213/0026

摘要： A CPU 80 controls data transfer from a first device to a second device in a kernel mode. A main memory 90 stores data to be transferred from the first device to the second device. The CPU 80 has: a first device control means 81 which controls the first device; a second device control means which controls the second device; and a data transfer control means 83 which makes a read instruction which instructs the first device control means 81 to store data read from the first device in the main memory 3, and makes a write instruction which instructs the second device control means 82 to write the data stored in the main memory 3 in the second device.

摘要翻译： CPU 80以内核模式控制从第一设备到第二设备的数据传输。 主存储器90存储要从第一设备传送到第二设备的数据。 CPU80具有：控制第一装置的第一装置控制装置81; 控制第二装置的第二装置控制装置; 以及数据传送控制装置83，其使得指令第一装置控制装置81将从第一装置读取的数据存储在主存储器3中的读取指令，并且进行指示第二装置控制装置82写入的写指令 存储在第二装置中的主存储器3中的数据。

公开(公告)号：US09882737B2

公开(公告)日：2018-01-30

申请号：US14003518

申请日：2012-01-19

申请人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

发明人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

IPC分类号： H04L12/40 ,  H04L12/26 ,  G06F13/38

CPC分类号： H04L12/40 ,  G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L43/0817

摘要： A network system of the present invention includes a computer and a device connected via a network, and a system management device. The computer and the device include, respectively, bridges that encapsulate transmission/reception data transmitted and received to and from each other and transmit and receive the data to and from each other via the network. Each of the bridges includes a control data transmitting means for generating control data for controlling the state of the system based on control auxiliary data issued from the computer or the device and used for controlling the state of the system, and transmitting the control data to the system management device via the network. The system management device includes a system controlling means for controlling the state of the system in accordance with the control data received thereby.

公开(公告)号：US20140059250A1

公开(公告)日：2014-02-27

申请号：US14003518

申请日：2012-01-19

申请人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

发明人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

IPC分类号： H04L12/40

CPC分类号： H04L12/40 ,  G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L43/0817

摘要： A network system of the present invention includes a computer and a device connected via a network, and a system management device. The computer and the device include, respectively, bridges that encapsulate transmission/reception data transmitted and received to and from each other and transmit and receive the data to and from each other via the network. Each of the bridges includes a control data transmitting means for generating control data for controlling the state of the system based on control auxiliary data issued from the computer or the device and used for controlling the state of the system, and transmitting the control data to the system management device via the network. The system management device includes a system controlling means for controlling the state of the system in accordance with the control data received thereby.

摘要翻译： 本发明的网络系统包括计算机和通过网络连接的设备和系统管理设备。 计算机和设备分别包括封装彼此发送和接收的发送/接收数据的网桥，并经由网络从彼此发送和接收数据。 每个桥包括控制数据发送装置，用于基于从计算机或设备发出的用于控制系统的状态的控制辅助数据产生用于控制系统的状态的控制数据，并将控制数据发送到 系统管理设备通过网络。 系统管理装置包括系统控制装置，用于根据从其接收的控制数据来控制系统的状态。

公开(公告)号：US08352667B2

公开(公告)日：2013-01-08

申请号：US12739843

申请日：2008-10-27

申请人： Jun Suzuki ,  Youichi Hidaka ,  Takashi Yoshikawa

发明人： Jun Suzuki ,  Youichi Hidaka ,  Takashi Yoshikawa

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  H04L41/0806 ,  H04L41/0853

摘要： Upstream network interfaces (2-1-2-N) and downstream network interfaces (5-1-5-M) have an upstream PCI-PCI bridge function and a downstream PCI-PCI bridge function, respectively. These network interfaces (2-1-2-N, 5-1-5-M) and a network (3) are incorporated in a system as a single multi-root PCI express switch. The network (3) tunnels TLPs (Transaction Layer Packets) between the upstream network interfaces (2-1-2-N) and the downstream network interfaces (5-1-5-M) or between the downstream network interfaces (5-1-5-M). This enables to distribute and connect a plurality of computers and a plurality of I/Os on a large scale without changing software, root complexes, and I/Os.

摘要翻译： 上游网络接口（2-1-2-N）和下游网络接口（5-1-5-M）分别具有上行PCI-PCI桥接功能和下游PCI-PCI桥接功能。 这些网络接口（2-1-2-N，5-1-5-M）和网络（3）作为单个多根PCI快速交换机并入系统中。 网络（3）在上游网络接口（2-1-2-N）和下游网络接口（5-1-5-M）之间或下游网络接口（5-1）之间隧道TLP（事务层报文） -5-M）。 这使得能够大规模地分发和连接多个计算机和多个I / O，而不需要改变软件，根机构和I / O。

公开(公告)号：US08352655B2

公开(公告)日：2013-01-08

申请号：US12007658

申请日：2008-01-14

申请人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Shigeyuki Yanagimachi ,  Takashi Yoshikawa

发明人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Shigeyuki Yanagimachi ,  Takashi Yoshikawa

IPC分类号： G06F13/00 ,  G06F3/00 ,  G06F13/42 ,  G06F13/36 ,  G06F13/20

CPC分类号： G06F13/387

摘要： A packet communication device autonomously selects an appropriate operation mode according to a connection environment to an external device before a service of the device is started. When the device is connected to the external buses, connection interface units notify an external device discrimination unit of connection of the device. The external device discrimination unit issues a polling packet to the connected device, discriminates the connected external device on the basis of the response packet, and notifies an operation mode switching unit. The operation mode switching unit selects an operation mode conforming to a connection environment of the packet communication device to the external device and switches the operation mode of the device to the mode. The selection of the operation modes is completed before the entire device or a portion of the device which is influenced by the selection of the operation mode starts a service to the external device to which the packet communication device is connected.

摘要翻译： 分组通信设备在开始服务设备之前，根据与外部设备的连接环境自主选择适当的操作模式。 当设备连接到外部总线时，连接接口单元通知设备连接的外部设备鉴别单元。 外部设备识别单元向所连接的设备发出轮询分组，基于响应分组来识别所连接的外部设备，并通知操作模式切换单元。 操作模式切换单元根据外部设备选择符合分组通信设备的连接环境的操作模式，并将设备的操作模式切换到该模式。 操作模式的选择在整个设备或受到选择操作模式影响的设备的一部分开始对分组通信设备连接到的外部设备的服务之前完成。

公开(公告)号：US20110064089A1

公开(公告)日：2011-03-17

申请号：US12992164

申请日：2009-05-18

申请人： Youichi Hidaka ,  Takashi Yoshikawa ,  Junichi Higuchi ,  Jun Suzuki

发明人： Youichi Hidaka ,  Takashi Yoshikawa ,  Junichi Higuchi ,  Jun Suzuki

IPC分类号： H04L12/56

CPC分类号： G06F13/4022

摘要： Provided are a first PCI-PCI bridge that handles Multi Root to connect to a plurality of root complexes; a second PCI-PCI bridge that connects to an endpoint; a virtual PCI Express switch that performs a switching process between the first and second PCI-PCI bridges; and a network control device that transfers data that is to be processed in the virtual PCI Express switch to an external switch through a network without passing through a PCI-PCI bridge.

摘要翻译： 提供了第一个PCI-PCI桥接器，其处理多根以连接到多个根复合体; 连接到端点的第二个PCI-PCI桥; 一个虚拟PCI Express交换机，执行第一和第二PCI-PCI桥之间的切换过程; 以及网络控制装置，其通过网络将通过网络将要在虚拟PCI Express交换机中处理的数据传送到外部交换机，而不通过PCI-PCI桥接器。

公开(公告)号：US09178665B2

公开(公告)日：2015-11-03

申请号：US13531637

申请日：2012-06-25

申请人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

发明人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

IPC分类号： H04L1/18 ,  H04L12/707 ,  H04L12/703 ,  H04L1/00

CPC分类号： H04L1/1841 ,  H04L1/1874 ,  H04L1/188 ,  H04L45/24 ,  H04L45/28 ,  H04L2001/0096

摘要： Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.

摘要翻译： 在多路径环境中只有一系列的序列号，任何分组丢失被非常快速地检测到，其中发射机和接收机通过多个网络彼此连接，当序列的任何 网络。 通信装置包括布置在每个网络处的多个序列缓冲器，用于累积分组，直到序列确认和不存在检测部分适于在所有序列缓冲器中累积一个或多个分组时确定是否存在分组。 利用这种安排，接收机的缺席检测部分监视保留在每个网络中的序列保证缓冲器中的数据包，注意发生分组丢失时分组存储在所有网络的序列缓冲器中的特性 。

公开(公告)号：US08233483B2

公开(公告)日：2012-07-31

申请号：US12200508

申请日：2008-08-28

申请人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

发明人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

IPC分类号： H04L12/28

CPC分类号： H04L1/1841 ,  H04L1/1874 ,  H04L1/188 ,  H04L45/24 ,  H04L45/28 ,  H04L2001/0096

摘要： Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.

摘要翻译： 在多路径环境中只有一系列的序列号，任何分组丢失被非常快速地检测到，其中发射机和接收机通过多个网络彼此连接，当序列的任何 网络。 通信装置包括布置在每个网络处的多个序列缓冲器，用于累积分组，直到序列确认和不存在检测部分适于在所有序列缓冲器中累积一个或多个分组时确定是否存在分组。 利用这种安排，接收机的不存在检测部分监视保留在每个网络中的序列保证缓冲器中的数据包，注意发生分组丢失时分组存储在所有网络的序列缓冲器中的特性 。

公开(公告)号：US20120110233A1

公开(公告)日：2012-05-03

申请号：US13382262

申请日：2010-06-11

申请人： Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

发明人： Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

IPC分类号： G06F13/20 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F2213/0026

摘要： Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself.

摘要翻译： 提高了容错能力，避免了I / O系统启动时的功能限制，缩短启动时间。 下游PCI Express桥接器设置连接到下游PCI Express桥本身的PCI Express设备，其中多个单根根兼容PCI Express设备由连接到多个上游PCI Express桥的多个根配置共享的多个单根根兼容PCI Express设备中， 下游PC Express桥本身通过网络，控制和监视与连接到下游PCI Express桥本身的PCI Express设备的物理链路的状态，并执行连接到下游的PCI Express设备的错误的监视和通知 PCI Express桥本身。