公开(公告)号：US5528545A

公开(公告)日：1996-06-18

申请号：US369758

申请日：1995-01-06

申请人： Jun Takahashi ,  Tomohisa Wada

发明人： Jun Takahashi ,  Tomohisa Wada

IPC分类号： G11C11/419 ,  G11C7/06

CPC分类号： G11C7/062

摘要： A semiconductor memory device includes a plurality of sense amplifiers for amplifying current changes which occur in corresponding bit line pairs in accordance with binary signals stored in activated memory cells. Each of the sense amplifiers includes first and second current mirror circuits for generating currents of the magnitudes respectively corresponding to currents flowing through a corresponding bit line pair, a storing circuit, responsive to a signal selecting a memory cell, for storing the currents generated by the first and second current mirror circuits before activation of the memory cell, or a difference between these currents, and a current supplying circuit, responsive to activation of the memory cell and based on the amount stored in the storing circuit, for supplying, to the first and second current mirror circuits, currents having a predetermined relationship with the currents having been generated by the first and second current mirror circuits before activation of the memory cell. A current change corresponding to data stored in the selected memory cell and not affected by an offset occurs in a connection node between the first current mirror circuit and the current supplying circuit, or a connection node between the second current mirror circuit and the current supplying circuit.

摘要翻译： 半导体存储器件包括多个读出放大器，用于根据存储在激活的存储器单元中的二进制信号放大在对应的位线对中发生的电流变化。 每个读出放大器包括第一和第二电流镜电路，用于产生分别对应于流过相应位线对的电流的电流的电流;存储电路，响应于选择存储器单元的信号，用于存储由 在存储单元激活之前的第一和第二电流镜电路，或这些电流之间的差异，以及电流供应电路，响应于存储单元的激活，并且基于存储在存储电路中的量，向第一 和第二电流镜电路，在存储单元激活之前，与由第一和第二电流镜电路产生的电流具有预定关系的电流。 在第一电流镜电路和电流供给电路之间的连接节点或第二电流镜电路和电流供给电路之间的连接节点上发生对应于存储在选择的存储单元中并且不受偏移影响的数据的电流变化 。

公开(公告)号：US07902481B2

公开(公告)日：2011-03-08

申请号：US11547323

申请日：2005-03-30

申请人： Keisuke Kigawa ,  Haruyuki Hiratsuka ,  Tomohisa Wada

发明人： Keisuke Kigawa ,  Haruyuki Hiratsuka ,  Tomohisa Wada

IPC分类号： H01L21/50 ,  B23K26/20

CPC分类号： H03H9/1021 ,  H01L21/50 ,  H03H3/02

摘要： A method of manufacturing a sealed electronic component, which can seal a housing in a high-vacuum state while preventing enclosure of a gas within the housing, as well as achieving the improvement in manufacturing efficiency. According to the method, after forming an unwelded section by a primary welding process step, including a first beam irradiation process step and a second beam irradiation process step, annealing treatment is performed in an annealing process step by irradiating an electron beam to a predetermined portion on a locus of the electron beam formed in the first beam irradiation process step. The locus may be on a housing or a lid.

摘要翻译： 一种制造密封电子部件的方法，其可以在高真空状态下密封壳体，同时防止气体在壳体内的封闭，以及实现制造效率的提高。 根据该方法，在通过一次焊接工艺步骤形成未焊接部分之后，包括第一光束照射处理步骤和第二光束照射处理步骤，在退火处理步骤中通过将电子束照射到预定部分 在第一光束照射处理步骤中形成的电子束的轨迹上。 轨迹可以在壳体或盖子上。

公开(公告)号：US06327188B1

公开(公告)日：2001-12-04

申请号：US09477560

申请日：2000-01-04

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C1300

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00 ,  G11C2207/2218 ,  G11C2207/2245

摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

摘要翻译： 与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。 保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。 在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。 比较器比较保持的内部地址信号和用于读取数据的内部地址信号。 如果它们之间发现匹配，则多路复用器从锁存电路输出数据以进行外部输出。 因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓存存储器的高速操作，并且实现诸如超级计算机， 大型计算器，工作站和个人计算机可以改进。

公开(公告)号：US5724292A

公开(公告)日：1998-03-03

申请号：US781386

申请日：1997-01-13

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C11/419 ,  G11C7/02

CPC分类号： G11C11/419

摘要： Sense circuits are provided correspondingly to bit line pairs provided corresponding to memory cell columns, respectively. The sense circuit senses, amplifies and latches storage data of the selected memory cell, and information latched by the sense amplifier is rewritten into the selected memory cell after selection of the memory cell. Thereby, destruction of storage information of the memory cell is prevented.

摘要翻译： 对应于分别对应于存储单元列提供的位线对提供感测电路。 感测电路感测，放大和锁存所选择的存储单元的存储数据，并且在选择存储单元之后，读出放大器锁存的信息被重写到所选存储单元中。 从而防止了存储单元的存储信息的破坏。

公开(公告)号：US5687111A

公开(公告)日：1997-11-11

申请号：US609313

申请日：1996-03-01

申请人： Tomohisa Wada ,  Kunihiko Kozaru ,  Toru Shiomi

发明人： Tomohisa Wada ,  Kunihiko Kozaru ,  Toru Shiomi

IPC分类号： G11C11/411 ,  G11C11/41 ,  G11C11/412 ,  G11C14/00 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00 ,  H01L27/02

CPC分类号： H01L27/1112 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903

摘要： A pair of driving bipolar transistors of a lateral type T1 and T2 have emitters coupled to a ground potential, collectors connected to a pair of highly resistive elements R1 and R2. Highly resistive elements R1 and R2 have respective other ends coupled to power supply potential V.sub.CC, and bases and collectors of transistors T1 and T2 are cross-connected to each other, thereby forming a flipflop circuit. Access MOS transistors Q3 and Q4 having a gate potential controlled by word line WL are each connected to form a conduction path between one of storage nodes A and B and one of the pair of bit lines BL and /BL.

摘要翻译： 横向型T1和T2的一对驱动双极晶体管具有耦合到接地电位的发射极，与一对高电阻元件R1和R2连接的集电极。 高电阻元件R1和R2具有耦合到电源电位VCC的相应的另一端，并且晶体管T1和T2的基极和集电极彼此交叉连接，从而形成触发电路。 具有由字线WL控制的栅极电位的接入MOS晶体管Q3和Q4分别被连接以形成存储节点A和B之一与一对位线BL和/ BL中的一个之间的导通路径。

公开(公告)号：US5546352A

公开(公告)日：1996-08-13

申请号：US354760

申请日：1994-12-12

申请人： Hirotoshi Sato ,  Tomohisa Wada

发明人： Hirotoshi Sato ,  Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/06 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C8/06

摘要： In the present invention, a row address processing circuit and a column address processing circuit operate in synchronism with an externally applied synchronous signal in a semiconductor memory device. The row address processing circuit and the column address processing circuit each include an address buffer and a decoder. The address buffer or decoder operates in synchronism with the synchronous signal.

摘要翻译： 在本发明中，行地址处理电路和列地址处理电路与半导体存储器件中外部施加的同步信号同步工作。 行地址处理电路和列地址处理电路各自包括地址缓冲器和解码器。 地址缓冲器或解码器与同步信号同步工作。

公开(公告)号：US5515325A

公开(公告)日：1996-05-07

申请号：US354767

申请日：1994-12-12

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C13/00

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00 ,  G11C2207/2218 ,  G11C2207/2245

摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculator, work station and personal computer can be improved.

摘要翻译： 与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。 保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。 在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。 比较器比较保持的内部地址信号和用于读取数据的内部地址信号。 如果在它们之间找到匹配，则多路复用器从锁存电路输出数据以进行外部输出。 因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓冲存储器的高速操作以及诸如超级计算机等各种级别的计算机的速度性能， 大型计算器，工作台和个人电脑可以改进。

公开(公告)号：US5487041A

公开(公告)日：1996-01-23

申请号：US309823

申请日：1994-09-21

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/84 ,  G11C29/832

摘要： A cache memory device includes a plurality of memory cell arrays each including a plurality of memory cell rows, a plurality of first fuse elements each provided corresponding to each memory cell row and disconnected when the corresponding memory cell row is defective, and a plurality of second fuse elements each provided corresponding to each memory cell array and disconnected when the corresponding memory cell array is defective. As a result, the cache memory device can indicate that, when a bit line of a certain memory cell array is defective, the memory cell array is defective by disconnecting a second fuse element corresponding to the memory cell array.

摘要翻译： 高速缓冲存储器装置包括多个存储单元阵列，每个存储单元阵列包括多个存储单元行，多个第一熔丝元件，每个第一熔丝元件对应于每个存储单元行设置，并且当相应的存储单元行有缺陷时被断开;多个第二熔丝元件 每个熔丝元件对应于每个存储单元阵列，并且当对应的存储单元阵列有缺陷时断开。 结果，高速缓冲存储器件可以指示当某个存储单元阵列的位线有缺陷时，通过断开与存储单元阵列相对应的第二熔丝元件，存储单元阵列有缺陷。

公开(公告)号：US5280441A

公开(公告)日：1994-01-18

申请号：US725782

申请日：1991-07-09

申请人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

发明人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

IPC分类号： G11C11/417 ,  G11C7/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  H01L27/108 ,  G11C5/06

CPC分类号： H01L27/10817 ,  G11C7/18

摘要： A plurality of bit line signal IO lines L1, /L1, . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

摘要翻译： 多个位线信号IO线L1，/ L1，...。 。 。 Ln和/ Ln布置在存储单元阵列上。 这些位线信号IO线被布置成与相应的位线BL1，/ BL1交叉。 。 。 BLn和/ BLn，分别连接到相应的位线。 每个位线信号IO线具有延伸到存储单元阵列的垂直于位线的方向的一端的端部，并且在端部耦合到位线外围电路。 尽管现有技术中位线外围电路只能位于位线的上端和下端，但位线外围电路也可以布置在本发明的位线信号IO线的端部。 这可以增加位线外围电路的布局的自由度，并且因此位线外围电路可以分散地布置在更大的区域中。

公开(公告)号：US4947374A

公开(公告)日：1990-08-07

申请号：US191115

申请日：1988-05-06

申请人： Tomohisa Wada ,  Shuji Murakami

发明人： Tomohisa Wada ,  Shuji Murakami

IPC分类号： G11C7/22 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C8/18

摘要： In a static random access memory, when address signals change, one-shot pulses are responsively generated. A detection signal obtained by ORing the one-shot pulses is employed as an equalize signal. Potentials of a bit line pair is equalized in response to the equalize signal. A write inhibiting signal having a pulse width larger than that of the equalize signal is generated by a pulse width increasing circuit. A write operation of data is inhibited in response to the write inhibiting signal.

摘要翻译： 在静态随机存取存储器中，当地址信号改变时，响应地产生单触发脉冲。 采用通过对单触发脉冲进行OR运算而获得的检测信号作为均衡信号。 位线对的电位响应均衡信号而相等。 通过脉冲宽度增加电路产生具有大于均衡信号的脉冲宽度的写禁止信号。 响应于写禁止信号，数据的写操作被禁止。