公开(公告)号：US07447086B2

公开(公告)日：2008-11-04

申请号：US11866261

申请日：2007-10-02

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S Gongwer

IPC分类号： G11C7/00

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US07295478B2

公开(公告)日：2007-11-13

申请号：US11127743

申请日：2005-05-12

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S. Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S. Gongwer

IPC分类号： G11C7/00

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20080019180A1

公开(公告)日：2008-01-24

申请号：US11866261

申请日：2007-10-02

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20060279990A1

公开(公告)日：2006-12-14

申请号：US11127743

申请日：2005-05-12

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20050128810A1

公开(公告)日：2005-06-16

申请号：US11049802

申请日：2005-02-03

申请人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

发明人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

摘要翻译： 以避免程序干扰的方式编程非易失性半导体存储器系统（或其他类型的存储器系统）。 在包括使用NAND架构的闪存系统的一个实施例中，通过在编程处理期间增加NAND串的源侧的沟道电位来避免程序干扰。 一个示例性实施方案包括将电压（例如Vdd）施加到源极触点，并且接通源抑制对应的单元的NAND极的源极侧选择晶体管。 另一种实施方案包括在施加编程电压之前，将预充电电压施加到对应于被禁止的单元的NAND串的未选择字线。

公开(公告)号：US07254071B2

公开(公告)日：2007-08-07

申请号：US11332567

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C29/00

CPC分类号： G11C16/0483 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C27/005 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US07457178B2

公开(公告)日：2008-11-25

申请号：US11331479

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C29/00

CPC分类号： G11C16/30 ,  G11C11/5628 ,  G11C16/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US20070159888A1

公开(公告)日：2007-07-12

申请号：US11332567

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C27/005 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US20060133156A1

公开(公告)日：2006-06-22

申请号：US11316475

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

公开(公告)号：US20060098494A1

公开(公告)日：2006-05-11

申请号：US11316119

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey Lutze ,  Jun Wan

IPC分类号： G11C16/04

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.