摘要:
In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.
摘要:
One embodiment of the present invention sets forth an active bit line charge keeper circuit for improving the reliability of a static random access memory (SRAM) circuit. The active bit line charge keeper circuit includes two sub-circuits, each disposed between bit line pairs within the SRAM circuit. The first sub-circuit mitigates residual state associated with over-developed read state on the bit lines. The second sub-circuit mitigates the effects of residual state associated with reading one value on a given pair of bit lines and subsequently writing a different value. By mitigating the effects of residual state within an SRAM circuit, higher reliability at a given performance level may be achieved.
摘要:
One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.
摘要:
One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from a low voltage domain to a high voltage domain, where VDDH is the supply voltage of the high voltage domain and VDDL is the supply voltage of the low voltage domain. A level shifting circuit uses a single input rather than dual rail inputs and does not produce a direct current flow in order to reduce the power consumption. The voltage level shifting circuit may also be used to shift a clock signal since the delays of the rising and falling edges of the clock signal are matched by using a delay element.
摘要:
One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.
摘要:
An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down.
摘要:
One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.
摘要:
An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.
摘要:
Embodiments for an area efficient high performance memory cell comprising a transistor connected to one of a bit line and a bit line bar are disclosed.
摘要:
One embodiment of the present invention sets forth a synchronous two-port static random access memory (SRAM) design with the area efficiency of a one-port SRAM. By restricting both access ports to an edge-triggered, synchronous clocking regime, the internal timing of the SRAM can be optimized to allow high-performance double-pumped access to the SRAM storage cells. By double-pumping the SRAM storage cells, one read access and one write access are possible per clock cycle, allowing the SRAM to present two external ports, each capable of performing one transaction per clock cycle.