公开(公告)号：US20130221218A1

公开(公告)日：2013-08-29

申请号：US13748183

申请日：2013-01-23

Applicant: Jun-Hee LEE ,  Yong-Ju KIM

Inventor： Jun-Hee LEE ,  Yong-Ju KIM

IPC: H01J37/26

CPC classification number: H01J37/261 ,  H01J37/265

Abstract: Provided is an electron microscope system using an augmented reality in that it recognizes a sample identification information by using an observation image generated through an electron microscope and the observation image is linked with the pre-set sample information according to the recognized sample identification information, so that an augmented reality image thereof is provided, thereby even the unskilled man can easily utilize the electron microscope and it can generate excitement about an education thereof.

Abstract translation: 提供一种使用增强现实的电子显微镜系统，其通过使用通过电子显微镜产生的观察图像来识别样本识别​​信息，并且观察图像根据所识别的样本识别信息与预设的样本信息相关联，因此 提供了增强的现实图像，从而即使不熟练的人也可以容易地利用电子显微镜，并且可以产生关于其教育的兴奋。

公开(公告)号：US20130051491A1

公开(公告)日：2013-02-28

申请号：US13333692

申请日：2011-12-21

Applicant: Yong-Ju KIM ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

Inventor： Yong-Ju KIM ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC: H04L25/49

CPC classification number: G06F13/4077

Abstract: A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.

Abstract translation: 用于发送数据的系统包括被配置为发送数据的多条数据线和被配置为将数据输出到数据线的发送芯片，并且响应于要通过数据发送的数据的数据模式执行串扰防止操作 数据线的线和阵列信息，以防止在数据线中发生串扰。

公开(公告)号：US20120194239A1

公开(公告)日：2012-08-02

申请号：US13111568

申请日：2011-05-19

Applicant: Jae-Min JANG ,  Yong-Ju KIM ,  Hae-Rang CHOI

Inventor： Jae-Min JANG ,  Yong-Ju KIM ,  Hae-Rang CHOI

IPC: H03L7/06

CPC classification number: H03L7/087 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816

Abstract: A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.

Abstract translation: DLL电路包括公共延迟线，其配置为通过响应于第一延迟控制代码或第二延迟控制代码选择性地将源时钟延迟一个或多个单位延迟来产生延迟锁定时钟，时钟周期检测器被配置为 源时钟的相位以延迟锁定时钟的相位处于周期检测模式，并且基于比较源极和延迟的相位的结果生成与源时钟的周期的延迟量相对应的第一延迟控制代码 锁定时钟，被配置为延迟延迟锁定时钟并输出反馈时钟的反馈延迟，以及延迟量控制器，被配置为将延迟锁定模式中的源时钟的相位与反馈时钟的相位进行比较，并且改变第二延迟 基于比较源和反馈时钟的结果的控制代码。

公开(公告)号：US20090257537A1

公开(公告)日：2009-10-15

申请号：US12344736

申请日：2008-12-29

Applicant: Yong-Ju KIM ,  Hae-Rang CHOI ,  Oh-Kyong KWON ,  Jun-Yong SONG ,  Min-Seok SHIN

Inventor： Yong-Ju KIM ,  Hae-Rang CHOI ,  Oh-Kyong KWON ,  Jun-Yong SONG ,  Min-Seok SHIN

IPC: H04L7/00

CPC classification number: H04L7/0338 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  H03K5/135

Abstract: A data recovery circuit that minimizes jitter during data transmission is presented. The data recovery circuit includes a data dividing unit, a data sampling unit, a data selecting unit, and a data recovery unit. The data dividing unit is for dividing external data to generate multiple-division data. The data sampling unit is for sampling the multiple-division data at a first time and a second time to generate sampling data. The data selecting unit is for selecting one of the data sampled at the first time or the second time from the sampling data in accordance to whether the sampling data is transited to output the selected one as selection data. The data recovery unit is for recovering the selection data to internal data in the same logic level as the logic level of the external data.

Abstract translation: 呈现数据传输中抖动最小化的数据恢复电路。 数据恢复电路包括数据分割单元，数据采样单元，数据选择单元和数据恢复单元。 数据分割单元用于分割外部数据以产生多分割数据。 数据采样单元用于在第一时间和第二时间对多分割数据进行采样以产生采样数据。 数据选择单元用于根据抽样数据是否被转换以输出所选择的数据作为选择数据，用于从采样数据中选择在第一时间或第二时间采样的数据中的一个。 数据恢复单元用于将选择数据恢复到与外部数据的逻辑电平相同的逻辑电平的内部数据。

公开(公告)号：US20100164568A1

公开(公告)日：2010-07-01

申请号：US12636901

申请日：2009-12-14

Applicant: Hae-Rang CHOI ,  Yong-Ju KIM ,  Sung-Woo HAN ,  Hee-Woong SONG ,  Ic-Su OH ,  Hyung-Soo KIM ,  Tae-Jin HWANG ,  Ji-Wang LEE ,  Jae-Min JANG ,  Chang-Kun PARK

Inventor： Hae-Rang CHOI ,  Yong-Ju KIM ,  Sung-Woo HAN ,  Hee-Woong SONG ,  Ic-Su OH ,  Hyung-Soo KIM ,  Tae-Jin HWANG ,  Ji-Wang LEE ,  Jae-Min JANG ,  Chang-Kun PARK

IPC: H03L7/00

CPC classification number: G11C19/28

Abstract: A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

Abstract translation: 可变延迟电路至少包括固定延迟单元，第一选择单元和可变延迟单元。 固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号，并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。 第一选择单元接收输入信号，第一延迟信号和第二延迟选择信号，并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。 可变延迟单元还接收表示第三延迟的第三延迟选择信号，并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。 第一个延迟是M个延迟单位的0或X倍。 第三延迟是从0到N个延迟单元中选择的延迟。

公开(公告)号：US20100164567A1

公开(公告)日：2010-07-01

申请号：US12347605

申请日：2008-12-31

Applicant: Yong-Ju KIM ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

Inventor： Yong-Ju KIM ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

IPC: H03L7/00 ,  G11C5/14 ,  G05F1/10

CPC classification number: G05F1/56 ,  G11C5/145 ,  H03L7/0812 ,  H03L7/093

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract translation: 内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器 被配置为产生具有与所述时钟比较器的输出信号相对应的电压电平的驱动控制电压; 以及配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。