公开(公告)号：US07746118B2

公开(公告)日：2010-06-29

申请号：US12281846

申请日：2007-09-11

申请人： Jung Bum Choi ,  Cang Keun Lee ,  Sang Jin Kim ,  Jae Ho Hwang

发明人： Jung Bum Choi ,  Cang Keun Lee ,  Sang Jin Kim ,  Jae Ho Hwang

IPC分类号： H03K19/20

CPC分类号： H03K19/20 ,  B82Y10/00 ,  H01L29/7613

摘要： The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs) having the same pattern and as many field effect transistors (FETs) as the number of the single electron transistors and performs operations on multi-valued signals using Coulomb oscillation that is the unique characteristic of SET to enable conversion of a single logic circuit to four basic logic circuits of NAND, OR, NOR and AND gates and a device using the same.

摘要翻译： 本发明涉及一种灵活的多功能逻辑电路，其使用具有相同图案和尽可能多的场效应晶体管（FET）的至少两个单电子晶体管（SET）将电流方向切换到串行或并行方向， 单电子晶体管，并且使用库仑振荡来执行多值信号的操作，该库仑振荡是SET的唯一特性，以使单个逻辑电路能够转换成NAND，或或非和与门的四个基本逻辑电路，以及使用该逻辑电路的器件 。

公开(公告)号：US20090251172A1

公开(公告)日：2009-10-08

申请号：US12281846

申请日：2007-09-11

申请人： Jung Bum Choi ,  Chang Keun Lee ,  Sang Jin Kim ,  Jae Ho Hwang

发明人： Jung Bum Choi ,  Chang Keun Lee ,  Sang Jin Kim ,  Jae Ho Hwang

IPC分类号： H03K19/173 ,  H01L29/00 ,  H03K19/0175

CPC分类号： H03K19/20 ,  B82Y10/00 ,  H01L29/7613

摘要： The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs) having the same pattern and as many field effect transistors (FETs) as the number of the single electron transistors and performs operations on multi-valued signals using Coulomb oscillation that is the unique characteristic of SET to enable conversion of a single logic circuit to four basic logic circuits of NAND, OR, NOR and AND gates and a device using the same.

摘要翻译： 本发明涉及一种灵活的多功能逻辑电路，其使用具有相同图案和尽可能多的场效应晶体管（FET）的至少两个单电子晶体管（SET）将电流方向切换到串行或并行方向， 单电子晶体管，并且使用库仑振荡来执行多值信号的操作，该库仑振荡是SET的唯一特性，以使单个逻辑电路能够转换成NAND，或或非和与门的四个基本逻辑电路，以及使用该逻辑电路的器件 。

公开(公告)号：US20130221330A1

公开(公告)日：2013-08-29

申请号：US13883321

申请日：2010-11-25

申请人： Jung Bum Choi ,  Jong Jin Lee

发明人： Jung Bum Choi ,  Jong Jin Lee

IPC分类号： H01L29/66

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/7613

摘要： The present invention relates to a multi-quantum dot device and a method of manufacturing the multi-quantum dot device. Further specifically, present invention relates to a multi-quantum dot device including a channel configured by patterning the top silicon layer of an SOI wafer to have a P-type silicon region formed by connecting a transversal region and a longitudinal region and a plurality of N-type silicon regions; gates including a plurality of tunneling barrier gates, an end of each tunneling barrier gate is positioned on the top of a transversal side of an intersection of the transversal region and the longitudinal region of the P-type silicon region to locally control a potential in the channel; a plurality of coupling gates, an end of each coupling gate is positioned on the top of a point between the intersection and another intersection adjacent to the intersection to locally control the potential in the channel; and a plurality of sensor gates, an end of each sensor gate is positioned on the top of a center of the intersection to sense a state of a quantum dot formed at the intersection; and an inversion layer gate formed on the top of the P-type silicon region to control free electron density.

摘要翻译： 本发明涉及一种多量子点装置及多量子点装置的制造方法。 更具体地说，本发明涉及一种多量子点器件，其包括通过对SOI晶片的顶部硅层进行构图而形成的沟道，以形成通过连接横向区域和纵向区域形成的P型硅区域和多个N 型硅区; 包括多个隧道势垒栅极的栅极，每个隧道势垒栅极的端部位于横向区域和P型硅区域的纵向区域的交叉的横向的顶部上，以局部地控制P型硅区域的电位 渠道; 多个耦合栅极，每个耦合栅极的端部位于交叉点和邻接相交处的另一交叉点之间的点的顶部，以局部地控制信道中的电位; 和多个传感器门，每个传感器门的端部位于交叉点的中心的顶部，以感测形成在交叉点处的量子点的状态; 以及形成在P型硅区域的顶部上以控制自由电子密度的反型层栅极。

公开(公告)号：US08178369B2

公开(公告)日：2012-05-15

申请号：US12444956

申请日：2007-10-08

申请人： Jung Bum Choi ,  Jong Jin Lee ,  Seung-Jun Shin ,  Rae-Sik Chung

发明人： Jung Bum Choi ,  Jong Jin Lee ,  Seung-Jun Shin ,  Rae-Sik Chung

IPC分类号： H01L21/00

CPC分类号： H01L21/32139 ,  B82Y10/00 ,  H01L21/0277 ,  H01L29/127 ,  H01L29/66439 ,  H01L29/7613

摘要： The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.

摘要翻译： 本发明涉及一种制造纳米级多结量子点器件的方法，其中它可以根据图案的数量或形状以及线宽来最小化约束，并且特别地，克服了取决于在图案之间发生的邻近效应的缺点，而 通过在图案之间形成新的导电层并将其用作新图案，最大限度地利用电子束光刻的优点。

公开(公告)号：US20100330751A1

公开(公告)日：2010-12-30

申请号：US12874146

申请日：2010-09-01

申请人： Jung Bum Choi ,  Seung Jun Shin

发明人： Jung Bum Choi ,  Seung Jun Shin

IPC分类号： H01L21/335

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  Y10S438/962 ,  Y10S977/762 ,  Y10S977/937

摘要： The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

摘要翻译： 本发明涉及在室温下工作的单电子晶体管（SET）及其制造方法，具体涉及在室温下工作的单电子晶体管及其制造方法，其为 能够最小化栅极电压对隧道势垒的影响并有效地控制量子点（QD）的电位，通过使用沟槽纳米线结构形成量子点并形成栅极围绕量子包裹大部分 点。

公开(公告)号：US20110174620A1

公开(公告)日：2011-07-21

申请号：US13063268

申请日：2009-10-08

申请人： Jung Bum Choi ,  Jong Jin Lee

发明人： Jung Bum Choi ,  Jong Jin Lee

IPC分类号： G01N33/68 ,  G01N27/447

CPC分类号： G01N33/588 ,  B01L3/502761 ,  B82Y5/00 ,  B82Y15/00 ,  C12Q1/6869 ,  G01N27/00 ,  G01N27/414 ,  G01N33/48721 ,  Y10S436/806 ,  C12Q2565/631 ,  C12Q2565/629 ,  C12Q2565/607

摘要： The present system relates to a system architecture that uses a single electron transistor (SET) to analyze base sequences of deoxyribonucleic acid (DNA) at ultra high speed in real time. DNA represents the entire body of genetic information and consists of nucleotide units. There are a total of four types of nucleotides, and each nucleotide consists of an identical pentose (deoxyribose), phosphate group, and one of four types of bases (Adenine: A, Guanine: G, Cytosine: C, Thymine: T). A and G are purines having a bicyclic structure while C and T are pyrimidines having a monocyclic structure. Each has a different atomic arrangement, which signifies a different charge distribution from one another. Therefore, a system comprising a single electron transistor that is very sensitive to charges, a probe of a very small size that reacts to one nucleotide very effectively, and an extended gate that connects the SET with the probe, can be used to analyze DNA base sequences at ultra high speed in real time.

摘要翻译： 本系统涉及使用单电子晶体管（SET）实时分析超高速脱氧核糖核酸（DNA）的碱基序列的系统架构。 DNA代表整个遗传信息，由核苷酸单位组成。 总共有四种类型的核苷酸，每个核苷酸由相同的戊糖（脱氧核糖），磷酸基和四种碱基之一（腺嘌呤：A，鸟嘌呤：G，胞嘧啶：C，胸腺嘧啶）组成。 A和G是具有双环结构的嘌呤，而C和T是具有单环结构的嘧啶。 每个都具有不同的原子排列，这表示彼此不同的电荷分布。 因此，可以使用包括对电荷非常敏感的单电子晶体管的系统，非常有效地对一个核苷酸反应的非常小的尺寸的探针和将SET连接到探针的扩展的门来分析DNA碱基 实时超高速序列。

公开(公告)号：US07981799B2

公开(公告)日：2011-07-19

申请号：US12305770

申请日：2008-09-11

申请人： Jung Bum Choi ,  Chang Keun Lee ,  Min Sik Kim

发明人： Jung Bum Choi ,  Chang Keun Lee ,  Min Sik Kim

IPC分类号： H01L21/44

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/66439

摘要： The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single-electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof.

摘要翻译： 本发明涉及室温操作的单电子器件及其制造方法，更具体地，涉及一种室温操作的单电子器件，其中将串联形成的多个金属硅化物点用作多个量子点 及其制造方法。

公开(公告)号：US20100157660A1

公开(公告)日：2010-06-24

申请号：US11993413

申请日：2006-09-11

申请人： Hun Woo Kye ,  Bok-Nam Song ,  Jung Bum Choi

发明人： Hun Woo Kye ,  Bok-Nam Song ,  Jung Bum Choi

IPC分类号： G11C11/24 ,  G11C7/00

CPC分类号： G11C11/565

摘要： Provided herein is an MV DRAM device capable of storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, wherein the gate of the transistor is connected to the ground voltage. According to the MV DRAM device of the present invention, since two or more multiple value data are stored in a cell, it is possible to increase the storage density of the device. In addition, since the MV DRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application.

摘要翻译： 本文提供了能够使用SET设备存储多个值级别的MV DRAM设备。 该装置包括一个或多个字线; 一个或多个位线; 连接到字线和位线的交点的DRAM单元; 电流源晶体管，其源极连接到电源电压，栅极和漏极连接到位线; 具有连接到位线的栅极和连接到接地电压的源极的SET（单电子晶体管）器件; 以及连接在SET设备的位线和漏极之间的晶体管，其中晶体管的栅极连接到接地电压。 根据本发明的MV DRAM装置，由于将两个以上的多值数据存储在单元中，因此可以提高装置的存储密度。 另外，由于MV DRAM器件仅需要使能字线才能重写数据，因此仅需要少量的电流，因此适用于低功率应用。

公开(公告)号：US08158538B2

公开(公告)日：2012-04-17

申请号：US12874146

申请日：2010-09-01

申请人： Jung Bum Choi ,  Seung Jun Shin

发明人： Jung Bum Choi ,  Seung Jun Shin

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/84

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  Y10S438/962 ,  Y10S977/762 ,  Y10S977/937

摘要： The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

摘要翻译： 本发明涉及在室温下工作的单电子晶体管（SET）及其制造方法，具体涉及在室温下工作的单电子晶体管及其制造方法，它们是 能够最小化栅极电压对隧道势垒的影响并有效地控制量子点（QD）的电位，通过使用沟槽纳米线结构形成量子点并形成栅极围绕量子包裹大部分 点。

公开(公告)号：US08031512B2

公开(公告)日：2011-10-04

申请号：US11993413

申请日：2006-09-11

申请人： Hun Woo Kye ,  Bok-Nam Song ,  Jung Bum Choi

发明人： Hun Woo Kye ,  Bok-Nam Song ,  Jung Bum Choi

IPC分类号： G11C11/24

CPC分类号： G11C11/565

摘要： Provided herein is an MV DRAM device for storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, where the gate of the transistor is connected to the ground voltage.

摘要翻译： 本文提供了一种用于使用SET设备存储多个值级别的MV DRAM设备。 该装置包括一个或多个字线; 一个或多个位线; 连接到字线和位线的交点的DRAM单元; 电流源晶体管，其源极连接到电源电压，栅极和漏极连接到位线; 具有连接到位线的栅极和连接到接地电压的源极的SET（单电子晶体管）器件; 以及连接在SET器件的位线和漏极之间的晶体管，其中晶体管的栅极连接到接地电压。