公开(公告)号：US20140211565A1

公开(公告)日：2014-07-31

申请号：US14165835

申请日：2014-01-28

Applicant: Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

Inventor： Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Abstract translation: 在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序 字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平 相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

公开(公告)号：US09343158B2

公开(公告)日：2016-05-17

申请号：US14165835

申请日：2014-01-28

Applicant: Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

Inventor： Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

IPC: G11C11/34 ,  G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Abstract translation: 在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序 字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平 相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

公开(公告)号：US09251878B2

公开(公告)日：2016-02-02

申请号：US14257072

申请日：2014-04-21

Applicant: Su-Yong Kim ,  Jinyub Lee ,  Seungjae Lee

Inventor： Su-Yong Kim ,  Jinyub Lee ,  Seungjae Lee

IPC: G11C16/06 ,  G11C8/08 ,  G11C11/408 ,  G11C16/08

CPC classification number: G11C8/08 ,  G11C11/4085 ,  G11C16/08

Abstract: A nonvolatile memory device comprises multiple memory blocks each comprising multiple memory cells arranged at intersections of wordlines and bitlines, an address decoder configured to electrically connect first lines to wordlines of one of the memory blocks in response to an address, a line selection switch circuit configured to electrically connect the first lines to second lines in different configurations according to the address, a first line decoder configured to provide the second lines with wordline voltages needed for driving, and a voltage generator configured to generate the wordline voltages.

Abstract translation: 非易失性存储器件包括多个存储器块，每个存储器块包括布置在字线和位线的交点处的多个存储器单元，地址解码器被配置为响应于地址将第一行电路连接到一个存储器块的字线，配置线路选择开关电路 根据地址将第一线路电连接到不同配置的第二线路，第一线路解码器，被配置为向第二线路提供用于驱动所需的字线电压;以及电压发生器，被配置为产生字线电压。

公开(公告)号：US09030869B2

公开(公告)日：2015-05-12

申请号：US13584847

申请日：2012-08-14

Applicant: Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

Inventor： Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

IPC: G11C11/34 ,  G11C7/22 ,  H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483

Abstract: A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

Abstract translation: 三维（3D）半导体存储器件包括存储单元串，每个存储单元串包括至少一个选择晶体管和至少一个存储单元，共享第一阱区的第一级晶体管组，并且包括连接到选择的第一选择线传输晶体管 晶体管和连接到存储单元的第一世界线传输晶体管，第二传输晶体管组共享第二阱区并且包括连接到选择晶体管的第二选择线传输晶体管，以及控制器，其控制第一传输晶体管组和 二级晶体管组。 控制器在读取操作期间将选择的电压施加到第一和第二阱区。