公开(公告)号：US20140211565A1

公开(公告)日：2014-07-31

申请号：US14165835

申请日：2014-01-28

Applicant: Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

Inventor： Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Abstract translation: 在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序 字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平 相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

公开(公告)号：US09343158B2

公开(公告)日：2016-05-17

申请号：US14165835

申请日：2014-01-28

Applicant: Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

Inventor： Jung-Ho Song ,  Su-Yong Kim ,  Sang-Won Hwang

IPC: G11C11/34 ,  G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Abstract translation: 在非易失性存储器件中编程包括通过至少两个程序步骤被编程成多个状态的多个存储器单元，相对于耦合到所选择的存储单元，从擦除电平到第一目标电平执行主程序 字线相对于耦合到所选择的字线的存储器单元与原始程序相关联地从擦除电平执行预编程电平，其中预编程电平大于擦除电平并小于第一目标电平 相对于耦合到所选字线的预编程存储器单元，从预编程级到第二目标级执行次程序。

公开(公告)号：US08446776B2

公开(公告)日：2013-05-21

申请号：US13022688

申请日：2011-02-08

Applicant: Sang-Won Hwang ,  Chan-Ho Kim

Inventor： Sang-Won Hwang ,  Chan-Ho Kim

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/3454

Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.

Abstract translation: 提供了一种用于非易失性存储器件的存储器单元的编程方法。 该方法包括基于编程电压，第一验证电压和第二验证电压来执行增量步进脉冲程序（ISPP）操作，并且基于存储器的第一通过失败结果来改变编程电压的增量值 基于第一验证电压产生第一通过失败结果。 基于存储单元的第二通过失败结果完成ISPP操作，基于第二验证电压生成第二通过失败结果。

公开(公告)号：US08295092B2

公开(公告)日：2012-10-23

申请号：US12498477

申请日：2009-07-07

Applicant: Chan-ho Kim ,  Sang-Won Hwang

Inventor： Chan-ho Kim ,  Sang-Won Hwang

IPC: G11C11/36 ,  G11C7/00

CPC classification number: G11C16/0483 ,  G11C7/12 ,  G11C16/24

Abstract: A nonvolatile memory device includes a plurality of memory cells connected to a wordline and arranged in a row direction, bitlines connected to the plurality of memory cells, respectively, and a bitline bias circuit configured to separately control bias voltages provided to the bitlines according to positions of the memory cells along the row direction.

Abstract translation: 非易失性存储器件包括连接到字线并沿行方向布置的多个存储器单元，分别连接到多个存储器单元的位线和位线偏置电路，其被配置为根据位置分别控制提供给位线的偏置电压 的存储单元沿着行方向。

公开(公告)号：US20120014187A1

公开(公告)日：2012-01-19

申请号：US13200361

申请日：2011-09-23

Applicant: Dae-Yong Kim ,  Sang-Won Hwang ,  Jun-Yong Park

Inventor： Dae-Yong Kim ,  Sang-Won Hwang ,  Jun-Yong Park

IPC: G11C16/06

CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract translation: 在一个实施例中，非易失性存储器件包括形成在衬底中的第一导电类型的阱以及与阱中形成的位线串联连接的第一多个存储单元晶体管。 在阱外部的衬底中形成缓冲器，并连接到位线。 至少一个去耦合晶体管被配置为从位线去耦合缓冲器，并且在阱中形成去耦合晶体管。

公开(公告)号：US07757153B2

公开(公告)日：2010-07-13

申请号：US11605977

申请日：2006-11-30

Applicant: Sang-Won Hwang ,  Jong-Soo Lee

Inventor： Sang-Won Hwang ,  Jong-Soo Lee

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/00 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A nonvolatile memory device, memory system and read method are disclosed. The memory device comprises a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, a page buffer configured to perform a read operation adapted to read data from the memory cell array and output read data, an error correction circuit configured to detect and correct an error in read data stored in a memory block K and generate corresponding error information, and a control circuit configured to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error information.

Abstract translation: 公开了非易失性存储器件，存储器系统和读取方法。 存储器件包括存储单元阵列，其包括多个存储器块，每个存储块具有适于存储N位的多个存储器单元，其中N是大于1的整数，被配置为执行适于从 存储单元阵列和输出读取数据，错误校正电路，被配置为检测和校正存储在存储块K中的读取数据中的错误并产生相应的错误信息;以及控制电路，被配置为减少存储在多个存储单元阵列中的位数 用于存储块K从N到J的存储器单元，其中J是小于N但大于零的整数，其响应于错误信息。

公开(公告)号：US07636265B2

公开(公告)日：2009-12-22

申请号：US11264168

申请日：2005-11-02

Applicant: Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

Inventor： Min-Gun Park ,  Jin-Wook Lee ,  Sang-Won Hwang

IPC: G11C7/00 ,  G11C7/22

CPC classification number: G11C16/3404

Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract translation: 提供了一种闪存器件，其包括适于将具有目标电压的编程电压提供给所选字线的高压发生器电路。 闪存器件适于根据在降低到目标电压之后的程序电压恢复到目标电压时终止编程间隔。 还提供了一种用于操作闪速存储器件的方法。

公开(公告)号：US20080209282A1

公开(公告)日：2008-08-28

申请号：US12003140

申请日：2007-12-20

Applicant: Jong-Soo Lee ,  Sang-Won Hwang

Inventor： Jong-Soo Lee ,  Sang-Won Hwang

IPC: G06F11/07

CPC classification number: G11C11/5621 ,  G11C11/56 ,  G11C16/04 ,  G11C29/00 ,  G11C29/42 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/0411 ,  G11C2211/5641 ,  G11C2229/723 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052

Abstract: One embodiment of the method includes determining a type of cells in a block of the flash memory if an error is detected in at least a portion of the block, and selectively changing one of a cell type indicator and a bad block indicator associated with the block based on the determined type of cells in the block. The cell type indicator indicates a type of the cells in the associated block, and the bad block indicator indicates whether the associated block is a usable block.

Abstract translation: 该方法的一个实施例包括：如果在块的至少一部分中检测到错误，则确定闪存的块中的小区的类型，并且选择性地改变与块相关联的小区类型指示符和坏块指示符之一 基于块中确定的细胞类型。 小区类型指示符指示相关块中的小区的类型，坏块指示符指示相关块是否是可用块。

公开(公告)号：US20110194353A1

公开(公告)日：2011-08-11

申请号：US13022688

申请日：2011-02-08

Applicant: Sang-Won Hwang ,  Chan-Ho Kim

Inventor： Sang-Won Hwang ,  Chan-Ho Kim

IPC: G11C16/10

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/3454

Abstract: A method of programming memory cells for a non-volatile memory device is provided. The method includes performing an incremental step pulse program (ISPP) operation based on a program voltage, a first verification voltage, and a second verification voltage, and changing an increment value of the program voltage based on a first pass-fail result of the memory cells, the first pass-fail result being generated based on the first verification voltage. The ISPP operation is finished based on a second pass-fail result of the memory cells, the second pass-fail result being generated based on the second verification voltage.

Abstract translation: 提供了一种用于非易失性存储器件的存储器单元的编程方法。 该方法包括基于编程电压，第一验证电压和第二验证电压来执行增量步进脉冲程序（ISPP）操作，并且基于存储器的第一通过失败结果来改变编程电压的增量值 基于第一验证电压产生第一通过失败结果。 基于存储单元的第二通过失败结果完成ISPP操作，基于第二验证电压生成第二通过失败结果。

公开(公告)号：US07911841B2

公开(公告)日：2011-03-22

申请号：US11606290

申请日：2006-11-30

Applicant: Sang-Won Hwang

Inventor： Sang-Won Hwang

IPC: G01R31/28 ,  G11C7/00

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C29/804 ,  G11C2211/5641

Abstract: A non-volatile memory may include a flag cell array, wherein each flag cell is arranged in the memory cell array interspersed among the plurality of memory cells. The flag cell array may include a plurality of flag cells indicating whether a corresponding row is MSB programmed. The non-volatile memory device performs an algorithm to read out data stored in the memory cell based on whether the memory cells of a row are MSB programmed. When determining whether the corresponding row is MSB programmed, a flag cell that is not normally operated may be replaced by a redundancy flag cell or data of the flag cell that is not normally operated may be excluded. Thus, the reliability in reading out of data and the production yield of the non-volatile memory may be improved.

Abstract translation: 非易失性存储器可以包括标志单元阵列，其中每个标志单元布置在散布在多个存储单元之间的存储单元阵列中。 标志单元阵列可以包括指示相应行是否被编程为MSB的多个标志单元。 非易失性存储器件基于一行的存储器单元是否被编程为MSB，执行读出存储在存储器单元中的数据的算法。 当确定对应的行是否被编程为MSB时，不正常操作的标志单元可以由冗余标志单元代替，或者可以排除不正常操作的标志单元的数据。 因此，可以提高读取数据的可靠性和非易失性存储器的生产率。