公开(公告)号：US09030869B2

公开(公告)日：2015-05-12

申请号：US13584847

申请日：2012-08-14

申请人： Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

发明人： Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

IPC分类号： G11C11/34 ,  G11C7/22 ,  H01L27/115 ,  G11C16/04

CPC分类号： H01L27/11582 ,  G11C16/0483

摘要： A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

摘要翻译： 三维（3D）半导体存储器件包括存储单元串，每个存储单元串包括至少一个选择晶体管和至少一个存储单元，共享第一阱区的第一级晶体管组，并且包括连接到选择的第一选择线传输晶体管 晶体管和连接到存储单元的第一世界线传输晶体管，第二传输晶体管组共享第二阱区并且包括连接到选择晶体管的第二选择线传输晶体管，以及控制器，其控制第一传输晶体管组和 二级晶体管组。 控制器在读取操作期间将选择的电压施加到第一和第二阱区。

公开(公告)号：US08472247B2

公开(公告)日：2013-06-25

申请号：US13157344

申请日：2011-06-10

申请人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

发明人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418

摘要： A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.

摘要翻译： 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。

公开(公告)号：US08570808B2

公开(公告)日：2013-10-29

申请号：US13186987

申请日：2011-07-20

申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

摘要： A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

摘要翻译： 非易失性存储器件包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压信号的电压发生器电路，以及 行选择电路，其将所述第一电压信号同时施加到所选择的字线，并将所述第二电压信号施加到未选择的字线。 所选择的字线和未选字线具有不同的电阻，而第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

公开(公告)号：US20120033501A1

公开(公告)日：2012-02-09

申请号：US13186987

申请日：2011-07-20

申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

摘要： Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

摘要翻译： 公开了一种非易失性存储器件，其包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压的电压发生器电路 信号和行选择电路，其将第一电压信号同时施加到所选字线，并将第二电压信号施加到未选字线。 所选择的字线和未选择的字线具有不同的电阻，但是第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

公开(公告)号：US10223011B2

公开(公告)日：2019-03-05

申请号：US15438644

申请日：2017-02-21

申请人： Hyejin Yim ,  Jinyub Lee ,  Kyung-Hwa Kang ,  Minseok Kim ,  Minsu Kim ,  Sung-Won Yun

发明人： Hyejin Yim ,  Jinyub Lee ,  Kyung-Hwa Kang ,  Minseok Kim ,  Minsu Kim ,  Sung-Won Yun

IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

摘要： A storage device includes a nonvolatile memory device and a controller configured to generate a read command according to a request of an external host device and transmit the read command to the nonvolatile memory device. The nonvolatile memory device is configured to perform a read operation in response to the read command, to output read data to the controller, and to store information of the read operation in an internal register.

公开(公告)号：US08654587B2

公开(公告)日：2014-02-18

申请号：US13920691

申请日：2013-06-18

申请人： ChiWeon Yoon ,  Donghyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

发明人： ChiWeon Yoon ,  Donghyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

摘要翻译： 非易失性存储器件通道升压方法，其中至少两个串连接到一个位线，所述通道升压方法包括将初始通道电压施加到所选存储器块中的串的通道，每个具有未编程的浮动禁止串 字符串之间的单元格，以及浮动禁止字符串的增强通道。

公开(公告)号：US20070268169A1

公开(公告)日：2007-11-22

申请号：US11804468

申请日：2007-05-18

申请人： Gwan-Bon Koo ,  Young-Bae Park ,  Sung-Won Yun

发明人： Gwan-Bon Koo ,  Young-Bae Park ,  Sung-Won Yun

IPC分类号： H03M3/00

CPC分类号： H03K17/0822 ,  H03K2017/0806

摘要： The present invention relates to a switch controlling apparatus. The switch controlling apparatus controls a main switch by using a first signal that corresponds to a current flowing to the main switch. The switch controlling apparatus includes a PWM controller for generating a control signal to control turning on/off of the main switch by using the first signal and a clock signal, and a TSD unit for changing the control signal corresponding to heat generated from the main switch. The TSD unit changes a response speed for the heat of the main switch by using the clock signal and the control signal.

摘要翻译： 开关控制装置技术领域本发明涉及开关控制装置。 开关控制装置通过使用与流过主开关的电流对应的第一信号来控制主开关。 开关控制装置包括PWM控制器，用于通过使用第一信号和时钟信号产生控制主开关的导通/截止的控制信号，以及TSD单元，用于改变与从主开关产生的热相对应的控制信号 。 TSD单元通过使用时钟信号和控制信号来改变主开关的热量的响应速度。

公开(公告)号：US08710806B2

公开(公告)日：2014-04-29

申请号：US13238565

申请日：2011-09-21

申请人： Sang Cheol Moon ,  Hyun Min Kim ,  Sung-Won Yun ,  Min-Woo Lee

发明人： Sang Cheol Moon ,  Hyun Min Kim ,  Sung-Won Yun ,  Min-Woo Lee

IPC分类号： H01M10/44 ,  H01M10/46

CPC分类号： H02M1/36 ,  H02M1/126 ,  H02M2001/322

摘要： A power supply includes an input filter and a discharging device. The input filter includes a capacitor to which an AC power source is provided. The discharging device rectifies and samples the AC power source. The discharging device generates a reference voltage according to a peak voltage of a generated sampling signal, generates an AC power source cutoff detection signal according to a comparison signal generated by comparing the sampling signal and a reference voltage, and discharges the capacitor through a discharging resistor according to the AC power source cutoff detection signal.

摘要翻译： 电源包括输入滤波器和放电装置。 输入滤波器包括提供有交流电源的电容器。 放电装置对交流电源进行整流和采样。 放电装置根据产生的采样信号的峰值电压产生参考电压，根据通过比较采样信号和参考电压产生的比较信号产生交流电源截止检测信号，并通过放电电阻放电电容器 根据交流电源切断检测信号。

公开(公告)号：US08289780B2

公开(公告)日：2012-10-16

申请号：US12792071

申请日：2010-06-02

申请人： Sung-Won Yun ,  Oh-suk Kwon

发明人： Sung-Won Yun ,  Oh-suk Kwon

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

摘要： A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.

摘要翻译： 页面缓冲器包括检测锁存器，数据锁存器和页面缓冲器控制器。 感测锁存器连接到位线，并且被配置为响应于感测锁存控制信号设置存储的数据，并且响应于在数据验证操作中施加到位线的信号来改变存储的数据。 数据锁存器被配置为存储要在编程操作中编程的多位数据，并且在数据验证操作中响应于数据锁存控制信号来设置存储的数据。 页缓冲器控制器被配置为在编程操作中根据存储在数据锁存器中的多位数据来控制位线，并且根据多位输出读出锁存控制信号和数据锁存控制信号 响应于数据验证操作中的控制信号而存储在数据锁存器中的数据。

公开(公告)号：US08164952B2

公开(公告)日：2012-04-24

申请号：US12719184

申请日：2010-03-08

申请人： Sung-Won Yun ,  Kihwan Choi

发明人： Sung-Won Yun ,  Kihwan Choi

IPC分类号： G11C16/04

CPC分类号： G11C11/5621 ,  G11C16/3436

摘要： A nonvolatile memory device comprises a memory cell array comprising a plurality of memory cells, a voltage generator configured to generate voltages to program the plurality of memory cells, and a control logic component configured to control the voltage generator to provide a plurality of program voltages to selected memory cells during successive iterations of a program loop. Wherein where memory cells corresponding to one logic state are judged to be program passed during a current iteration of the program loop, the control logic component controls the voltage generator such that a program voltage corresponding to the one logic state is skipped during subsequent iterations of the program loop.

摘要翻译： 非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，被配置为产生用于编程多个存储器单元的电压的电压发生器，以及控制逻辑元件，被配置为控制电压发生器以提供多个编程电压 在程序循环的连续迭代期间选择存储单元。 其中对应于一个逻辑状态的存储器单元在程序循环的当前迭代期间被判断为程序传递，控制逻辑部件控制电压发生器，使得在随后的迭代期间跳过对应于一个逻辑状态的编程电压 程序循环。