公开(公告)号：US20130319516A1

公开(公告)日：2013-12-05

申请号：US13633175

申请日：2012-10-02

申请人： Jung-Wu Chien ,  Chuan-Chi Chen

发明人： Jung-Wu Chien ,  Chuan-Chi Chen

IPC分类号： H01L31/0224 ,  H01L31/18

CPC分类号： H01L31/022433 ,  H01L31/0504 ,  Y02E10/50

摘要： A method for manufacturing a front electrode of a solar cell and a solar cell device manufactured by the same method are provided. The method includes steps of providing a substrate; performing a first screen printing process to form at least one first electrode over the substrate; and performing a second screen printing process to form at least one row of a second electrode structure over the substrate. The first electrode is formed with a strip body and a plurality of salients connected to the strip body. The second electrode structure has a plurality of sections of finger electrodes, wherein first ends of the finger electrodes directly contact with first surfaces of the salients of the first electrode, respectively, without extending to the strip body.

摘要翻译： 提供了一种制造太阳能电池的前电极的方法和通过相同的方法制造的太阳能电池装置。 该方法包括提供衬底的步骤; 执行第一丝网印刷工艺以在所述基底上形成至少一个第一电极; 以及执行第二丝网印刷处理以在所述基底上形成至少一行第二电极结构。 第一电极形成有带状体和连接到条状体的多个凸起。 第二电极结构具有多个指状电极部分，其中指状电极的第一端分别与第一电极的凸起的第一表面直接接触，而不延伸到带状体。

公开(公告)号：US07435645B2

公开(公告)日：2008-10-14

申请号：US11164060

申请日：2005-11-09

申请人： Jung-Wu Chien

发明人： Jung-Wu Chien

IPC分类号： H01L21/336

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L29/66181

摘要： A dynamic random access memory (DRAM) includes a substrate, an active device and a deep trench capacitor. A trench and a deep trench are formed in the substrate. The active device is disposed on the substrate. The active device includes a gate structure and a doped region. The gate structure is disposed on the substrate and fills the trench. The doped region is disposed in the substrate at a first side of the gate structure. The deep trench capacitor is disposed in the deep trench of the substrate at a second side of the gate, and the second side is opposite to the first side. In addition, an upper electrode of the deep trench capacitor is adjacent to the bottom of the trench.

摘要翻译： 动态随机存取存储器（DRAM）包括衬底，有源器件和深沟槽电容器。 在衬底中形成沟槽和深沟槽。 有源器件设置在衬底上。 有源器件包括栅极结构和掺杂区域。 栅极结构设置在衬底上并填充沟槽。 掺杂区域设置在栅极结构的第一侧的衬底中。 深沟槽电容器设置在栅极的第二侧的衬底的深沟槽中，第二侧与第一侧相对。 此外，深沟槽电容器的上电极与沟槽的底部相邻。

公开(公告)号：US07871884B2

公开(公告)日：2011-01-18

申请号：US12195365

申请日：2008-08-20

申请人： Jung-Wu Chien

发明人： Jung-Wu Chien

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L29/66181

摘要： A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure.

摘要翻译： 一种用于制造DRAM的方法包括首先提供形成图案化的第一掩模层和被图案化的第一掩模层暴露的深沟槽的衬底。 深沟槽电容器形成在深沟槽中，并且每个深沟槽电容器包括下电极，上电极和电容器介电层。 在第一掩模层和衬底中形成器件隔离层，用于限定有源区。 去除第一掩模层以暴露衬底，并且在暴露的衬底上形成半导体层。 图案化半导体层和衬底以形成沟槽，并且沟槽的底部与沟槽电容器的上部电极相邻。 填充到沟槽中的栅极结构形成在衬底上。 掺杂区域形成在与栅极结构的一侧相邻的衬底中。

公开(公告)号：US07479452B2

公开(公告)日：2009-01-20

申请号：US11104213

申请日：2005-04-12

申请人： Jung-Wu Chien

发明人： Jung-Wu Chien

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76897 ,  H01L27/10885 ,  H01L27/10894

摘要： A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

摘要翻译： 在本发明中公开了一种形成电池位线接触插塞的方法。 在提供具有第一区域和第二区域的半导体衬底之后，在第一区域形成单元位线触点。 在第二区域形成位线图形开口之后，在单元位线触点和位线图形开口的侧壁上形成多个间隔物。 然后在第二区域的开口内形成衬底接触和栅极接触。 通过进行蚀刻工艺在每个基板接触和栅极接触之间形成沟槽之后，形成电池 - 位线接触插塞，基板接触插塞和栅极接触插头。

公开(公告)号：US20080138970A1

公开(公告)日：2008-06-12

申请号：US11670427

申请日：2007-02-02

申请人： Jung-Wu Chien

发明人： Jung-Wu Chien

IPC分类号： H01L21/28

CPC分类号： H01L29/66621 ,  H01L21/28061 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66583

摘要： A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.

公开(公告)号：US07348622B2

公开(公告)日：2008-03-25

申请号：US11445847

申请日：2006-06-02

申请人： Chao-Hsi Chung ,  Jung-Wu Chien

发明人： Chao-Hsi Chung ,  Jung-Wu Chien

IPC分类号： H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10867

摘要： A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

摘要翻译： 存储器电荷存储节点（120.1,120.2,120.3）至少部分地位于沟槽（124）中。 存储器包括晶体管，其包括存在于沟槽的第一侧（124.1）但不是第二侧（124.2）的源/漏区（170）。 在形成提供电荷存储节点的至少一部分的导电材料（120.3）之前，邻近第二侧（124.2）形成阻挡特征（704）以阻挡导电材料（120.3）。 阻挡特征可以是最终结构中的电介质，或者可以是在导电材料沉积之后去除以使电介质留下空间的牺牲特征。 可以使用包括多个直条的掩模（710）来对存储器阵列中的多个沟槽的阻挡特征进行图案化，每个直条在行方向上贯穿存储器阵列。 电荷存储节点在邻近源极/漏极区的沟槽的第一侧具有突起（120.3），并且还具有横向邻近突起的顶表面部分（T）。 沟槽侧壁在上表面部分（T）上方具有在第二侧（124.2）上的基本上直的部分（S）。 沟槽侧壁上的电介质（144.1,144.2,188）具有在第二侧比在沟槽的第一侧更厚的部分（188）。

公开(公告)号：US07232719B2

公开(公告)日：2007-06-19

申请号：US11092150

申请日：2005-03-28

申请人： Chao-Hsi Chung ,  Jung-Wu Chien

发明人： Chao-Hsi Chung ,  Jung-Wu Chien

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/10867

摘要： A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.

摘要翻译： 存储器电荷存储节点（120.1,120.2,120.3）至少部分地位于沟槽（124）中。 存储器包括晶体管，其包括存在于沟槽的第一侧（124.1）但不是第二侧（124.2）的源/漏区（170）。 在形成提供电荷存储节点的至少一部分的导电材料（120.3）之前，邻近第二侧（124.2）形成阻挡特征（704）以阻挡导电材料（120.3）。 阻挡特征可以是最终结构中的电介质，或者可以是在导电材料沉积之后去除以使电介质留下空间的牺牲特征。 可以使用包括多个直条的掩模（710）来对存储器阵列中的多个沟槽的阻挡特征进行图案化，每个直条在行方向上贯穿存储器阵列。 电荷存储节点在邻近源极/漏极区的沟槽的第一侧具有突起（120.3），并且还具有横向邻近突起的顶表面部分（T）。 沟槽侧壁在上表面部分（T）上方具有在第二侧（124.2）上的基本上直的部分（S）。 沟槽侧壁上的电介质（144.1,144.2,188）具有在第二侧比在沟槽的第一侧更厚的部分（188）。

公开(公告)号：US20070085152A1

公开(公告)日：2007-04-19

申请号：US11250822

申请日：2005-10-14

申请人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

发明人： Douglas Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC分类号： H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

摘要翻译： 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

公开(公告)号：US20080268646A1

公开(公告)日：2008-10-30

申请号：US12168748

申请日：2008-07-07

申请人： Douglas Blaine Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

发明人： Douglas Blaine Butler ,  Chia-Shun Hsiao ,  Jung-Wu Chien ,  Chih-Hsun Chu

IPC分类号： H01L21/311

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

摘要翻译： 一种缩小面积动态随机存取存储器（DRAM）单元及其制造方法，其中通过沿着第一图案形成侧壁间隔物，通过两个光刻间距占据小于一个光刻间距的区域，以限定活动的第一部分 存储单元的区域和第二正交定向图案，以限定存储单元的有源区域的第二部分，从而为存储单元的列创建梯形有源区域。

公开(公告)号：US20060228852A1

公开(公告)日：2006-10-12

申请号：US11104213

申请日：2005-04-12

申请人： Jung-Wu Chien

发明人： Jung-Wu Chien

IPC分类号： H01L21/8244 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76897 ,  H01L27/10885 ,  H01L27/10894

摘要： A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.