公开(公告)号：US20110159662A1

公开(公告)日：2011-06-30

申请号：US12979775

申请日：2010-12-28

申请人： Chao-Hsi CHUNG

发明人： Chao-Hsi CHUNG

IPC分类号： H01L21/02

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： A method for fabricating a crown-shaped capacitor includes providing a first dielectric layer with a protective pillar formed thereover, including a first conductive layer, a protective layer, and a mask layer. A second conductive layer is formed over a sidewall of the protective pillar. A first capacitance layer and a third conductive layer are formed over the first dielectric layer. A sacrificial layer is formed over the third conductive layer. The sacrificial layer, the third conductive layer, the first capacitance layer, the second conductive layer, and the mask layer above the protective layer are partially removed. The second conductive layer and the third conductive are removed to form a recess adjacent to the first capacitance layer. The protective layer is removed and an opening is formed to expose the first and second conductive layers. A second capacitance layer and a fourth conductive layer are formed in the opening. The sacrificial layer is removed to expose the third conductive layer.

摘要翻译： 一种用于制造冠状电容器的方法包括：提供具有形成在其上的保护柱的第一介电层，包括第一导电层，保护层和掩模层。 在保护柱的侧壁上形成第二导电层。 第一电容层和第三导电层形成在第一介电层上。 牺牲层形成在第三导电层上。 部分地去除了保护层上方的牺牲层，第三导电层，第一电容层，第二导电层和掩模层。 去除第二导电层和第三导体以形成与第一电容层相邻的凹部。 去除保护层并形成开口以暴露第一和第二导电层。 第二电容层和第四导电层形成在开口中。 去除牺牲层以暴露第三导电层。

公开(公告)号：US20070246763A1

公开(公告)日：2007-10-25

申请号：US11460346

申请日：2006-07-27

申请人： Chao-Hsi Chung

发明人： Chao-Hsi Chung

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42376 ,  H01L27/10873 ,  H01L29/1037 ,  H01L29/4933 ,  H01L29/66651 ,  H01L29/66659

摘要： A trench step channel cell transistor and a manufacture method thereof are disclosed. The transistor could be applied to increase the channel length thereof. The transistor comprises a step silicon layer formed by a selective growth, while the step silicon layer is located above the active area of the transistor.

摘要翻译： 公开了一种沟槽级沟道单元晶体管及其制造方法。 可以施加晶体管以增加其沟道长度。 晶体管包括通过选择性生长形成的阶梯硅层，而步进硅层位于晶体管的有源区之上。

公开(公告)号：US20070212839A1

公开(公告)日：2007-09-13

申请号：US11308928

申请日：2006-05-26

申请人： Chao-Hsi Chung ,  Wen-Shuo Kuo

发明人： Chao-Hsi Chung ,  Wen-Shuo Kuo

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/7682 ,  H01L21/76879

摘要： A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate. A plurality of gate structures are formed on the gate dielectric layer. Each of the gate structures is composed of a stacked structure and a spacer. Each stacked structure includes a gate conductive layer and a cap layer. The spacer includes a first dielectric layer and a second dielectric layer. A barrier layer is formed over the substrate covering conformally the gate structures and the gate dielectric layer. A dielectric layer is formed on the barrier layer. A self-aligned contact window etching process is conducted to form a contact window opening. A SEG process is conducted to grow an epitaxial silicon layer to form a contact window and an air gap in the opening.

摘要翻译： 对半导体装置的制造方法进行说明。 在基板上形成栅极电介质层。 在栅极电介质层上形成多个栅极结构。 每个栅极结构由堆叠结构和间隔物组成。 每个堆叠结构包括栅极导电层和盖层。 间隔件包括第一介电层和第二介电层。 阻挡层形成在覆盖保护栅极结构和栅极电介质层的衬底上。 在阻挡层上形成介电层。 进行自对准的接触窗蚀刻工艺以形成接触窗口。 进行SEG工艺以生长外延硅层以在开口中形成接触窗口和气隙。

公开(公告)号：US20070090436A1

公开(公告)日：2007-04-26

申请号：US11565633

申请日：2006-12-01

申请人： Chao-Hsi Chung

发明人： Chao-Hsi Chung

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： A deep trench capacitor disposed in a deep trench in a substrate is provided. The deep trench capacitor includes a bottom electrode disposed in the substrate surrounding a bottom of the deep trench; a first conductive layer disposed in the deep trench; a capacitor dielectric layer disposed between a lower surface of the deep trench and the first conductive layer; a second conductive layer disposed in the deep trench and above the first conductive layer; a collar oxide layer disposed between an upper surface of the deep trench and the second conductive layer; a third conductive layer disposed in the deep trench and above the second conductive layer; an isolation structure disposed in parts of the third conductive layer, the second conductive layer and the substrate; and an isolation layer disposed below the isolation structure and in parts of the second conductive layer and the substrate.

摘要翻译： 提供了设置在衬底中的深沟槽中的深沟槽电容器。 深沟槽电容器包括设置在衬底中的底部电极，围绕深沟槽的底部; 布置在所述深沟槽中的第一导电层; 设置在所述深沟槽的下表面和所述第一导电层之间的电容器电介质层; 设置在所述深沟槽中并位于所述第一导电层上方的第二导电层; 设置在所述深沟槽的上表面和所述第二导电层之间的环状氧化物层; 设置在所述深沟槽中并位于所述第二导电层上方的第三导电层; 设置在所述第三导电层，所述第二导电层和所述基板的一部分中的隔离结构; 以及隔离层，其设置在隔离结构的下方以及第二导电层和基板的一部分中。

公开(公告)号：US20060051916A1

公开(公告)日：2006-03-09

申请号：US10904479

申请日：2004-11-12

申请人： Chao-Hsi Chung

发明人： Chao-Hsi Chung

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. A collar oxide layer is formed on the sidewall of the deep trench exposed by the first conductive layer. A second conductive layer fills each deep trench. An opening is formed in a region predetermined for an isolation structure between adjacent deep trenches, wherein the depth of the opening is greater than that of the isolation structure. An isolation layer is filled in the opening.

摘要翻译： 制造深沟槽电容器的方法包括在衬底中形成多个深沟槽。 底部电极形成在每个深沟槽的底部周围的基板中。 在每个深沟槽的底部形成电容器电介质层和第一导电层。 在由第一导电层暴露的深沟槽的侧壁上形成环状氧化物层。 第二导电层填充每个深沟槽。 在相邻深沟槽之间的隔离结构预定的区域中形成开口，其中开口的深度大于隔离结构的深度。 隔离层填充在开口中。

公开(公告)号：US20050074943A1

公开(公告)日：2005-04-07

申请号：US10707357

申请日：2003-12-08

申请人： SU-CHEN LAI ,  CHAO-HSI CHUNG

发明人： SU-CHEN LAI ,  CHAO-HSI CHUNG

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/1087

摘要： A method of fabricating a deep trench capacitor is provided. A substrate with a deep trench thereon is provided. A bottom electrode is formed at a bottom of the deep trench and a capacitor dielectric layer, a first conductive layer, a protective layer and a collar layer are sequentially formed on the surface of the deep trench. The protective layer and the collar oxide layer on the surface of the first conductive layer are removed, material is deposited into the deep trench to form a material layer. A portion of the material layer is removed to form a first opening. Thereafter, collar oxide layer and the protective layer not covered by the material layer is removed. A portion of the mask layer and the protective layer on the sidewall of the first opening is removed to form a second opening. After removing the material layer, a second conductive layer and a third conductive layer are sequentially formed in the deep trench.

摘要翻译： 提供一种制造深沟槽电容器的方法。 提供其上具有深沟槽的衬底。 底部电极形成在深沟槽的底部，并且在深沟槽的表面上依次形成电容器电介质层，第一导电层，保护层和套环层。 去除第一导电层表面上的保护层和环氧化物层，将材料沉积到深沟槽中以形成材料层。 去除材料层的一部分以形成第一开口。 此后，去除环氧化物层和未被材料层覆盖的保护层。 去除掩模层的一部分和第一开口的侧壁上的保护层以形成第二开口。 在去除材料层之后，在深沟槽中依次形成第二导电层和第三导电层。

公开(公告)号：US6074291A

公开(公告)日：2000-06-13

申请号：US250952

申请日：1999-02-16

申请人： Wen-Tung Chang ,  Chao-Hsi Chung

发明人： Wen-Tung Chang ,  Chao-Hsi Chung

IPC分类号： B24B37/30 ,  B24B41/06

CPC分类号： B24B37/30

摘要： An apparatus for preparing an ultra-thin specimen with a polishing wheel is developed. The apparatus includes a base, a holding unit mounted on the base and having a movable part for supporting the specimen, and an adjusting assembly attached to the base for adjusting an orientation of the specimen relative to a top surface of the polishing wheel by providing a fine movement during polishing. The movable part of the holding unit is advantageously moved away from the adjusting assembly to enlarge the latitudinal cross-section of the apparatus so as to increase the precision of the orientation.

摘要翻译： 开发了一种用抛光轮制备超薄样品的设备。 该装置包括基座，保持单元，其安装在基座上并具有用于支撑试件的可移动部分，以及附接到基座的调节组件，用于通过提供试样相对于抛光轮的顶表面来调整样本的取向 抛光过程中精细的动作。 保持单元的可移动部分有利地远离调节组件移动，以扩大装置的纬度横截面，从而提高取向的精度。

公开(公告)号：US07163858B2

公开(公告)日：2007-01-16

申请号：US10904479

申请日：2004-11-12

申请人： Chao-Hsi Chung

发明人： Chao-Hsi Chung

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. A collar oxide layer is formed on the sidewall of the deep trench exposed by the first conductive layer. A second conductive layer fills each deep trench. An opening is formed in a region predetermined for an isolation structure between adjacent deep trenches, wherein the depth of the opening is greater than that of the isolation structure. An isolation layer is filled in the opening.

摘要翻译： 制造深沟槽电容器的方法包括在衬底中形成多个深沟槽。 底部电极形成在每个深沟槽的底部周围的基板中。 在每个深沟槽的底部形成电容器电介质层和第一导电层。 在由第一导电层暴露的深沟槽的侧壁上形成环状氧化物层。 第二导电层填充每个深沟槽。 在相邻深沟槽之间的隔离结构预定的区域中形成开口，其中开口的深度大于隔离结构的深度。 隔离层填充在开口中。

公开(公告)号：US20080032471A1

公开(公告)日：2008-02-07

申请号：US11580807

申请日：2006-10-13

申请人： Wen-Shuo Kuo ,  Chao-Hsi Chung ,  Yung Yao Lee ,  Hui-Min Li

发明人： Wen-Shuo Kuo ,  Chao-Hsi Chung ,  Yung Yao Lee ,  Hui-Min Li

IPC分类号： H01L21/8242

CPC分类号： H01L21/76224 ,  H01L27/1087

摘要： A method for manufacturing a shallow trench isolation structure in a deep trench and application thereof are provided, wherein the deep trench having an upper electrode and an insulation layer on the upper electrode is formed in a substrate which has a pad insulation layer. The method comprises the following steps: forming a hard mask on the first insulation layer, doping a first portion of the hard mask, removing the undoped portion of the hard mask to expose a portion of the first insulation layer and reserve the first portion of the hard mask, removing the exposed portion of the first insulation layer to expose a portion of the upper electrode, and forming a conductive layer on the exposed portion of the upper electrode wherein a predetermined distance exists between the upper surface of the conductive layer and the pad insulation layer.

摘要翻译： 提供一种在深沟槽中制造浅沟槽隔离结构的方法及其应用，其中在具有衬垫绝缘层的衬底中形成具有上电极和上电极上的绝缘层的深沟槽。 该方法包括以下步骤：在第一绝缘层上形成硬掩模，掺杂硬掩模的第一部分，去除硬掩模的未掺杂部分以暴露第一绝缘层的一部分并保留第一绝缘层的第一部分 去除所述第一绝缘层的暴露部分以暴露所述上电极的一部分，以及在所述上电极的暴露部分上形成导电层，其中在所述导电层的所述上表面和所述焊盘之间存在预定距离 绝缘层。

公开(公告)号：US20060220089A1

公开(公告)日：2006-10-05

申请号：US11445847

申请日：2006-06-02

申请人： Chao-Hsi Chung ,  Jung-Wu Chien

发明人： Chao-Hsi Chung ,  Jung-Wu Chien

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10867

摘要： A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.3) at the first side of the trench adjacent to the source/drain region and also has a top surface portion (T) laterally adjacent to the protrusion. The trench sidewall has a substantially straight portion (S) on the second side (124.2) rising above the top surface portion (T). The dielectric (144.1, 144.2, 188) on the trench sidewall has a portion (188) which is thicker on the second side than on the first side of the trench.