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    APPARATUS AND METHOD FOR IMPROVED LOCK ELISION TECHNIQUES
    5.
    发明申请
    APPARATUS AND METHOD FOR IMPROVED LOCK ELISION TECHNIQUES 有权
    改进的锁定技术的装置和方法

    公开(公告)号：US20150074366A1

    公开(公告)日：2015-03-12

    申请号：US14024451

    申请日：2013-09-11

    申请人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

    发明人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

    IPC分类号： G06F9/46 ,  G06F12/14

    CPC分类号： G06F9/467 ,  G06F9/30181 ,  G06F9/526 ,  G06F12/1466

    摘要： An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.

    摘要翻译： 一种用于提高在事务存储架构内执行投机关键部分的效率的装置和方法。 例如，根据一个实施例的方法包括：等待执行程序代码的推测性临界部分，直到当前事务释放锁定为止; 在检测到锁已经被释放时响应地执行推测性关键部分以完成，而不管在推测性关键部分的执行期间锁是否被另一事务持有; 一旦投机关键部分的执行完成，确定是否采取锁定; 如果不采取锁定，则提交投机性关键部分，如果采取锁定，则中止推测性关键部分。

    Enabling Maximum Concurrency In A Hybrid Transactional Memory System
    6.
    发明申请
    Enabling Maximum Concurrency In A Hybrid Transactional Memory System 有权
    在混合事务内存系统中启用最大并发性

    公开(公告)号：US20150277967A1

    公开(公告)日：2015-10-01

    申请号：US14225804

    申请日：2014-03-26

    申请人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

    发明人： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

    IPC分类号： G06F9/46 ,  G06F12/10

    CPC分类号： G06F9/467 ,  G06F9/528

    摘要： In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.

    摘要翻译： 在事务性存储器系统的实施例中，一种装置包括处理器和执行逻辑，以使得能够并行执行第一软件交易模式和第二软件交易模式的第二软件交易的至少一个第一软件交易，并且至少一个 第一硬件事务模式的硬件事务和第二硬件事务模式的至少一个第二硬件事务。 在一个示例中，执行逻辑可以在处理器内实现。 描述和要求保护其他实施例。

    UNBOUNDED TRANSACTIONAL MEMORY WITH FORWARD PROGRESS GUARANTEES USING A HARDWARE GLOBAL LOCK
    8.
    发明申请
    UNBOUNDED TRANSACTIONAL MEMORY WITH FORWARD PROGRESS GUARANTEES USING A HARDWARE GLOBAL LOCK 有权
    使用硬件全局锁定的前进进程保护的无关紧要的交易记忆

    公开(公告)号：US20150169362A1

    公开(公告)日：2015-06-18

    申请号：US14108892

    申请日：2013-12-17

    申请人： Justin E. Gottschlich ,  Irina Calciu ,  Tatiana Shpeisman ,  Gilles A. Pokam

    发明人： Justin E. Gottschlich ,  Irina Calciu ,  Tatiana Shpeisman ,  Gilles A. Pokam

    IPC分类号： G06F9/46 ,  G06F12/14

    CPC分类号： G06F9/467 ,  G06F9/52 ,  G06F9/528

    摘要： A processing device implementing unbounded transactional memory with forward progress guarantees using a hardware global lock is disclosed. A processing device of the disclosure includes a hardware transactional memory (HTM) hardware contention manager to cause a bounded transaction to be translated to an unbounded transaction, the unbounded transaction to acquire a global hardware lock for the unbounded transaction, the global hardware lock read by bounded transactions that abort when the global hardware lock is taken. The processing device further includes an execution unit communicably coupled to the HTM hardware contention manager to execute instructions of the unbounded transaction without speculation, the unbounded transaction to release the global hardware lock upon completion of execution of the instructions.

    摘要翻译： 公开了一种使用硬件全局锁来实现具有前进进度的无界事务存储器的处理设备。 本公开的处理装置包括硬件事务存储器（HTM）硬件竞争管理器，用于使有界事务被转换为无界事务，该无界事务获取无界事务的全局硬件锁，全局硬件锁由 全局硬件锁定时中止的有界事务。 处理装置还包括执行单元，其可通信地耦合到HTM硬件争用管理器以执行无界事务的指令而无需推测，该无限制事务在完成指令的执行时释放全局硬件锁定。

    APPARATUS AND METHOD FOR A PROFILER FOR HARDWARE TRANSACTIONAL MEMORY PROGRAMS
    9.
    发明申请
    APPARATUS AND METHOD FOR A PROFILER FOR HARDWARE TRANSACTIONAL MEMORY PROGRAMS 有权
    用于硬件交易记忆程序的配置文件的装置和方法

    公开(公告)号：US20160179569A1

    公开(公告)日：2016-06-23

    申请号：US14581772

    申请日：2014-12-23

    申请人： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu

    发明人： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu

    IPC分类号： G06F9/46 ,  G06F9/45 ,  G06F9/30 ,  G06F12/08 ,  G06F9/445

    CPC分类号： G06F9/467 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/44563 ,  G06F11/3632 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084

    摘要： An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional debugger (TDB) recording module to record data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code; and a profiler to analyze portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code.

    摘要翻译： 描述了用于硬件事务存储器（HTM）分析器的装置和方法。 例如，设备的一个实施例包括事务调试器（TDB）记录模块，用于记录与事务存储器程序代码的执行有关的数据，包括与事务存储器程序代码中的分支和事务事件的执行相关的数据; 以及分析器，用于使用基于跟踪的重放技术来分析记录数据的部分，以响应地生成包括事务级事件和可用于优化事务存储器程序代码的功能级冲突数据的简档数据。