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    Method of system for detecting abnormal interleavings in concurrent programs
    2.
    发明授权
    Method of system for detecting abnormal interleavings in concurrent programs 有权
    在并发程序中检测异常交错的系统方法

    公开(公告)号：US08862942B2

    公开(公告)日：2014-10-14

    申请号：US13498613

    申请日：2011-09-29

    申请人： Nicholas A. Jalbert ,  Cristiano L. Pereira ,  Gilles A. Pokam

    发明人： Nicholas A. Jalbert ,  Cristiano L. Pereira ,  Gilles A. Pokam

    IPC分类号： G06F11/00 ,  G06F11/36 ,  G06F11/14 ,  G06F9/38

    CPC分类号： G06F11/1479 ,  G06F9/3851 ,  G06F11/3632

    摘要： A method and system for detecting abnormal interleavings in a multi-threaded program includes generating an execution log in response to execution of the multi-threaded program. Based on the execution log, a list of allowable immediate interleavings is generated if the execution of the multi-threaded program resulted in no concurrency errors and a list of suspicious immediate interleavings is generated if the execution of the multi-threaded program resulted in one or more concurrency errors. The first and second lists are compared to generate a list of error-causing immediate interleavings. A replayable core is then generated and executed based on the list of error-causing immediate interleavings.

    摘要翻译： 一种用于检测多线程程序中的异常交织的方法和系统，包括响应于多线程程序的执行而生成执行日志。 基于执行日志，如果多线程程序的执行导致没有并发错误，并且如果多线程程序的执行导致一个或多个程序执行，则生成可疑立即交织列表，则生成允许的立即交织的列表 更多的并发错误。 将第一和第二列表进行比较以产生造成误差的立即交错的列表。 然后基于造成错误的即时交错的列表来生成并执行可重放的核心。

    METHOD OF SYSTEM FOR DETECTING ABNORMAL INTERLEAVINGS IN CONCURRENT PROGRAMS
    3.
    发明申请
    METHOD OF SYSTEM FOR DETECTING ABNORMAL INTERLEAVINGS IN CONCURRENT PROGRAMS 有权
    用于检测同步程序中异常交互的系统方法

    公开(公告)号：US20130297978A1

    公开(公告)日：2013-11-07

    申请号：US13498613

    申请日：2011-09-29

    申请人： Nicholas A. Jalbert ,  Cristiano L. Pereira ,  Gilles A. Pokam

    发明人： Nicholas A. Jalbert ,  Cristiano L. Pereira ,  Gilles A. Pokam

    IPC分类号： G06F11/14

    CPC分类号： G06F11/1479 ,  G06F9/3851 ,  G06F11/3632

    摘要： A method and system for detecting abnormal interleavings in a multi-threaded program includes generating an execution log in response to execution of the multi-threaded program. Based on the execution log, a list of allowable immediate interleavings is generated if the execution of the multi-threaded program resulted in no concurrency errors and a list of suspicious immediate interleavings is generated if the execution of the multi-threaded program resulted in one or more concurrency errors. The first and second lists are compared to generate a list of error-causing immediate interleavings. A replayable core is then generated and executed based on the list of error-causing immediate interleavings.

    摘要翻译： 一种用于检测多线程程序中的异常交织的方法和系统，包括响应于多线程程序的执行而生成执行日志。 基于执行日志，如果多线程程序的执行导致没有并发错误，并且如果多线程程序的执行导致一个或多个程序执行，则生成可疑立即交织列表，则生成允许的立即交织的列表 更多的并发错误。 将第一和第二列表进行比较以产生造成误差的立即交错的列表。 然后基于造成错误的即时交错的列表来生成并执行可重放的核心。

    TECHNOLOGIES FOR ROOT CAUSE IDENTIFICATION OF USE-AFTER-FREE MEMORY CORRUPTION BUGS
    5.
    发明申请
    TECHNOLOGIES FOR ROOT CAUSE IDENTIFICATION OF USE-AFTER-FREE MEMORY CORRUPTION BUGS 有权
    技术因素导致无使用内存损坏BUG的识别

    公开(公告)号：US20160283302A1

    公开(公告)日：2016-09-29

    申请号：US14670863

    申请日：2015-03-27

    申请人： Justin E. Gottschlich ,  Gilles A. Pokam ,  Cristiano L. Pereira

    发明人： Justin E. Gottschlich ,  Gilles A. Pokam ,  Cristiano L. Pereira

    IPC分类号： G06F11/07

    CPC分类号： G06F11/079 ,  G06F11/073

    摘要： Technologies for identification of a potential root cause of a use-after-free memory corruption bug of a program include a computing device to replay execution of the execution of the program based on an execution log of the program. The execution log comprises an ordered set of executed instructions of the program that resulted in the use-after-free memory corruption bug. The computing device compares a use-after-free memory address access of the program to a memory address associated with an occurrence of the use-after-free memory corruption bug in response to detecting the use-after-free memory address access and records the use-after-free memory address access of the program as a candidate for a root cause of the use-after-free memory corruption bug to a candidate list in response to detecting a match between the use-after-free memory address access of the program and the memory address associated with the occurrence of the use-after-free memory corruption bug.

    摘要翻译： 用于识别程序的无使用存储器内存损坏错误的潜在根本原因的技术包括基于程序的执行日志来重放执行程序的计算设备。 执行日志包括导致使用随机存储器损坏错误的程序的执行指令的有序集合。 计算装置响应于检测到使用无存储器存储器地址访问而将程序的无用空闲存储器地址访问与与使用无释放存储器损坏错误的发生相关联的存储器地址进行比较，并且记录 响应于检测到所述无用存储器内存地址访问之间的匹配，将所述程序的无用空闲内存地址访问作为候选列表的候选者，作为所述无用存储器内存损坏错误的根本原因 程序和与使用随机存储器内存损坏错误的发生相关联的存储器地址。

    MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS
    6.
    发明申请
    MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS 有权
    促进计算机系统软件程序中指导性原子动力的动态和有效管理的机制

    公开(公告)号：US20140281705A1

    公开(公告)日：2014-09-18

    申请号：US13977690

    申请日：2013-03-15

    申请人： Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne

    发明人： Nathan D. Dautenhahn ,  Justin E. Gottschlich ,  Gilles Pokam ,  Cristiano L. Pereira ,  Shiliang Hu ,  Klaus Danne

    IPC分类号： G06F11/14

    CPC分类号： G06F9/30145 ,  G06F9/3009 ,  G06F9/3895 ,  G06F9/3897 ,  G06F9/52 ,  G06F11/0724 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3636

    摘要： A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

    摘要翻译： 描述了根据一个实施例的用于促进软件程序中的指令原子性违规的动态和有效管理的机制。 如本文所述的实施例的方法包括在来自记录系统的重放逻辑处接收运行第一宏指令的第一软件线程的记录和运行第二宏指令的第二软件线程。 第一软件线程和第二软件线程分别由计算设备处理器的第一核心和第二核心执行。 记录系统可以记录第一和第二宏指令之间的交织。 该方法包括在发生时准确地重播第一和第二宏指令的交错记录。 正确重放可以包括重播第一和第二宏指令的本地存储器状态以及第一和第二软件线程的全局存储器状态。

    TECHNIQUES FOR DETECTING RACE CONDITIONS
    9.
    发明申请
    TECHNIQUES FOR DETECTING RACE CONDITIONS 审中-公开
    检测条件的技术

    公开(公告)号：US20160232077A1

    公开(公告)日：2016-08-11

    申请号：US15026515

    申请日：2013-12-12

    申请人： Shiliang HU ,  Gilles A. POKAM ,  Cristiano L. PEREIRA ,  Justin E. GOTTSCHLICH

    发明人： Shiliang HU ,  Gilles A. POKAM ,  Cristiano L. PEREIRA ,  Justin E. GOTTSCHLICH

    IPC分类号： G06F11/36

    CPC分类号： G06F11/3632 ,  G06F9/526 ,  G06F11/0715 ,  G06F11/0778 ,  G06F11/30 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3466 ,  G06F11/366

    摘要： Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.

    摘要翻译： 各种实施例通常涉及通过检测与这种访问相关联的所选择的高速缓存事件的发生来检测由应用程序的不同部分的未协调数据访问引起的竞争条件。 一种装置包括处理器组件; 触发组件，用于由处理器组件执行以配置处理器组件的监控单元以检测与对一条数据的访问之间的竞争条件相关联的高速缓存事件，并且捕获处理器组件的状态的指示以生成监视 响应于缓存事件的发生的数据; 以及用于由处理器组件执行以配置监视单元的计数器的计数器组件，以使得能够以小于高速缓存事件的每次出现的频率捕获处理器组件的状态的指示。 描述和要求保护其他实施例。

    PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE
    10.
    发明申请
    PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE 有权
    具有记录仪记录器的处理器，用于记录多个软件中的螺纹交叉

    公开(公告)号：US20140189256A1

    公开(公告)日：2014-07-03

    申请号：US13729718

    申请日：2012-12-28

    申请人： TIM KRANICH ,  GILLES A. POKAM ,  JUSTIN E. GOTTSCHLICH ,  KLAUS DANNE ,  ROLF KASSA ,  SHILIANG HU ,  CRISTIANO L. PEREIRA

    发明人： TIM KRANICH ,  GILLES A. POKAM ,  JUSTIN E. GOTTSCHLICH ,  KLAUS DANNE ,  ROLF KASSA ,  SHILIANG HU ,  CRISTIANO L. PEREIRA

    IPC分类号： G06F12/08

    CPC分类号： G06F9/526 ,  G06F11/3404 ,  G06F11/3409 ,  G06F11/3471 ,  G06F11/36 ,  G06F11/3636

    摘要： A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

    摘要翻译： 处理器包括执行第一软件线程的第一核，执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。 该逻辑包括存储器访问监视器逻辑，以监视第一线程对存储器的访问，记录被监视的访问的存储器地址，以及检测与其他线程相关的记录存储器地址的数据比赛。 逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。 每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。 块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。 块缓冲区是临时存储块，直到块被从处理器传出。