PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE
    5.
    发明申请
    PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE 有权
    具有记录仪记录器的处理器,用于记录多个软件中的螺纹交叉

    公开(公告)号:US20140189256A1

    公开(公告)日:2014-07-03

    申请号:US13729718

    申请日:2012-12-28

    Abstract: A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

    Abstract translation: 处理器包括执行第一软件线程的第一核,执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。 该逻辑包括存储器访问监视器逻辑,以监视第一线程对存储器的访问,记录被监视的访问的存储器地址,以及检测与其他线程相关的记录存储器地址的数据比赛。 逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。 每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。 块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。 块缓冲区是临时存储块,直到块被从处理器传出。

    METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
    7.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION 有权
    方法,系统和设备的尺寸扩展

    公开(公告)号:US20090172344A1

    公开(公告)日:2009-07-02

    申请号:US11967868

    申请日:2007-12-31

    Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

    Abstract translation: 方法,系统和装置可以对存储器中固定的多个页面的固定的多个页表条目进行初始化,每个页面具有第一大小,其中每个页表条目的线性地址对应于物理地址,固定多个 的页面对齐。 可以将针对对齐的页面的每个页表条目中的一个位设置为指示固定的多个页面是否被视为具有大于第一页面大小的第二页面大小的一个组合页面。 描述和要求保护其他实施例。

    APPARATUS AND METHOD FOR EFFICIENT REGISTER ALLOCATION AND RECLAMATION
    8.
    发明申请
    APPARATUS AND METHOD FOR EFFICIENT REGISTER ALLOCATION AND RECLAMATION 审中-公开
    装置和方法,用于有效的注册分配和恢复

    公开(公告)号:US20160266901A1

    公开(公告)日:2016-09-15

    申请号:US14643855

    申请日:2015-03-10

    Abstract: A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.

    Abstract translation: 描述了用于有效的寄存器回收的方法和装置。 例如,设备的一个实施例包括:单次使用检测和标记逻辑,用于检查指令序列,以检测由具有一次使用的指令序列使用的逻辑寄存器,并且如果指令是将指令标记为单个使用指令 是具有单次使用的逻辑寄存器的消费者; 分配器,用于分配处理器资源来执行所述指令序列,所述处理器资源包括映射到逻辑寄存器的物理寄存器,以执行所述指令序列; 并且响应于检测到由指令标记逻辑提供的标签来注册回收逻辑以释放单个使用寄存器的逻辑到物理映射。

    Data alignment for telecommunications networks
    9.
    发明授权
    Data alignment for telecommunications networks 失效
    电信网络的数据调整

    公开(公告)号:US07188290B2

    公开(公告)日:2007-03-06

    申请号:US10128134

    申请日:2002-04-23

    Applicant: Rolf Kassa

    Inventor: Rolf Kassa

    CPC classification number: H04J3/0608

    Abstract: An alignment module receives a sequence of un-aligned data words, finds a frame alignment word, and aligns the data words based on the position of the frame alignment word in the un-aligned data words. Comparators compare segments of two consecutive un-aligned data words to a frame alignment word and generate a first logic signal when there is a match. A shift register and a counter are used to determine which comparator generates the first logic signal. The counter sends a count to a barrel shifter, which shifts the un-aligned data words according to the count to generate aligned data words.

    Abstract translation: 对准模块接收一系列不对齐的数据字,找到一个帧对齐字,并根据帧排列字在未排列数据字中的位置对齐数据字。 比较器将两个连续的非对齐数据字的段与帧对准字进行比较,并在存在匹配时产生第一逻辑信号。 使用移位寄存器和计数器来确定哪个比较器产生第一逻辑信号。 计数器向桶形移位器发送计数,该移位器根据计数移位不对齐的数据字,以生成对齐的数据字。

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