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公开(公告)号:US20230091827A1
公开(公告)日:2023-03-23
申请号:US17692711
申请日:2022-03-11
Applicant: Kioxia Corporation
Inventor: Satoshi NAGASHIMA , Hidenori MIYAGAWA , Atsushi TAKAHASHI , Shota KASHIYAMA
IPC: H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
Abstract: A semiconductor memory device includes a substrate, a semiconductor layer extending in a first direction, a first conductive layer extending in a second direction and opposed to the semiconductor layer, an electric charge accumulating layer disposed between the semiconductor layer and the first conductive layer, and a first contact electrode extending in the first direction and connected to the first conductive layer. The first contact electrode has one end in the first direction farther from the substrate than the first conductive layer, the other end in the first direction closer to the substrate than the first conductive layer. The first conductive layer includes a first part opposed to the semiconductor layer and a second part connected to the first contact electrode. The second part has a thickness in the first direction larger than a thickness in the first direction of the first part.
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公开(公告)号:US20220172957A1
公开(公告)日:2022-06-02
申请号:US17651326
申请日:2022-02-16
Applicant: Kioxia Corporation
Inventor: Atsushi TAKAHASHI
IPC: H01L21/311 , H01L21/67
Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes etching the first film with first gas including carbon and fluorine to form a concave portion in the first film and form a second film in the concave portion. The method further includes treating the second film by using the second film to second gas or second liquid, wherein the second film is treated without plasma.
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公开(公告)号:US20220336492A1
公开(公告)日:2022-10-20
申请号:US17850699
申请日:2022-06-27
Applicant: KIOXIA CORPORATION
Inventor: Yuta SAITO , Shinji MORI , Atsushi TAKAHASHI , Toshiaki YANASE , Keiichi SAWA , Kazuhiro MATSUO , Hiroyuki YAMASHITA
IPC: H01L27/11582 , H01L21/02 , H01L29/04
Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.
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公开(公告)号:US20210296347A1
公开(公告)日:2021-09-23
申请号:US17017385
申请日:2020-09-10
Applicant: Kioxia Corporation
Inventor: Yuta SAITO , Shinji MORI , Keiji HOSOTANI , Daisuke HAGISHIMA , Atsushi TAKAHASHI
IPC: H01L27/11578 , H01L27/11565 , H01L27/11568
Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer; first and second insulating layers in contact with the first semiconductor layer; a second semiconductor layer in contact with the first insulating layer; a third semiconductor layer in contact with the second insulating layer; a first conductor; a third insulating layer in contact with the first conductor; a fourth insulating layer provided between the second semiconductor layer and the third insulating layer; a first charge storage layer provided between the second semiconductor layer and the fourth insulating layer; and a fifth insulating layer provided between the second semiconductor layer and the first charge storage layer. The second semiconductor layer, the first conductor, the third to fifth insulating layers, and the first charge storage layer function as a first memory cell.
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公开(公告)号:US20210013225A1
公开(公告)日:2021-01-14
申请号:US16809887
申请日:2020-03-05
Applicant: Kioxia Corporation
Inventor: Yuta SAITO , Shinji MORI , Atsushi TAKAHASHI , Toshiaki YANASE , Keiichi SAWA , Kazuhiro MATSUO , Hiroyuki YAMASHITA
IPC: H01L27/11582 , H01L29/04 , H01L21/02
Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.
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公开(公告)号:US20220246640A1
公开(公告)日:2022-08-04
申请号:US17659881
申请日:2022-04-20
Applicant: KIOXIA CORPORATION
Inventor: Keiichi SAWA , Kazuhiro MATSUO , Kazuhisa MATSUDA , Hiroyuki YAMASHITA , Yuta SAITO , Shinji MORI , Masayuki TANAKA , Kenichiro TORATANI , Atsushi TAKAHASHI , Shouji HONDA
IPC: H01L27/11582 , H01L27/11578 , H01L27/11519
Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.
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公开(公告)号:US20220238345A1
公开(公告)日:2022-07-28
申请号:US17471684
申请日:2021-09-10
Applicant: Kioxia Corporation
Inventor: Atsushi TAKAHASHI , Ayata HARAYAMA , Yuya NAGATA
IPC: H01L21/3065 , H01J37/305 , H01L21/306
Abstract: A manufacturing method for a semiconductor device according to an embodiment includes performing first etching for forming a recess in a layer to be processed using a reactive ion etching method, performing a first treatment of supplying a silylation agent to the recess after the first etching, and performing second etching of etching at least a bottom surface of the recess using a reactive ion etching method after the first treatment.
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公开(公告)号:US20220076961A1
公开(公告)日:2022-03-10
申请号:US17173287
申请日:2021-02-11
Applicant: Kioxia Corporation
Inventor: Atsushi TAKAHASHI
IPC: H01L21/311 , H01L21/67
Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes etching the first film with first gas including carbon and fluorine to form a concave portion in the first film and form a second film in the concave portion. The method further includes treating the second film by using the second film to second gas or second liquid, wherein the second film is treated without plasma.
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公开(公告)号:US20220406611A1
公开(公告)日:2022-12-22
申请号:US17643543
申请日:2021-12-09
Applicant: Kioxia Corporation
Inventor: Atsushi TAKAHASHI , Tsubasa IMAMURA , Wu LI , Yuto ITAGAKI , Minki CHOU
IPC: H01L21/3065 , H01J37/32 , H01L21/02
Abstract: A method for manufacturing a semiconductor device according to an embodiment is a method for manufacturing a semiconductor device including performing a first etching process of forming a recess in a layer to be processed formed on a substrate by reactive ion etching using a first gas, performing a first process of supplying hydrogen radicals to the recess by using a second gas containing hydrogen in a state where a temperature of the substrate is equal to or more than 200° C. and equal to or less than 350° C. after the first etching process, and performing a second etching process of etching a bottom surface of the recess by reactive ion etching using a third gas after the first process.
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