公开(公告)号：US12028068B2

公开(公告)日：2024-07-02

申请号：US18178038

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Fumiya Watanabe ,  Toshifumi Watanabe ,  Kazuhiko Satou ,  Shouichi Ozaki ,  Kenro Kubota ,  Atsuko Saeki ,  Ryota Tsuchiya ,  Harumi Abe

IPC: H03K3/011 ,  G11C7/10 ,  H03K17/14 ,  H03K19/20

CPC classification number: H03K3/011 ,  G11C7/1048 ,  H03K17/14 ,  G11C2207/2254 ,  H03K19/20

Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

公开(公告)号：US11495308B2

公开(公告)日：2022-11-08

申请号：US17202661

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Junya Matsuno ,  Kenro Kubota ,  Masato Dome ,  Kensuke Yamamoto ,  Kei Shiraishi ,  Kazuhiko Satou ,  Ryo Fukuda ,  Masaru Koyanagi

IPC: G11C16/32 ,  G11C16/04 ,  H01L27/115 ,  G11C16/08 ,  G11C16/26

Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.

公开(公告)号：US11209846B2

公开(公告)日：2021-12-28

申请号：US16941801

申请日：2020-07-29

Applicant: Kioxia Corporation

Inventor： Kazuhiko Satou ,  Tomonori Kurosawa ,  Dai Nakamura

IPC: G05F1/46 ,  G05F1/648

Abstract: In one embodiment, a semiconductor device includes a reference voltage supply circuit configured to supply a first reference voltage and a second reference voltage. The device further includes a power source voltage supply circuit including a first power source voltage generator supplied with the first reference voltage and configured to generate a first power source voltage, and a second power source voltage generator supplied with the second reference voltage and configured to generate a second power source voltage, the power source voltage supply circuit being configured to supply the first power source voltage and the second power source voltage to a power source voltage line. The device further includes a voltage control circuit connected to the power source voltage line, and configured to control a value of the first reference voltage and a value the second reference voltage.

公开(公告)号：US12033704B2

公开(公告)日：2024-07-09

申请号：US17952659

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Junya Matsuno ,  Kenro Kubota ,  Masato Dome ,  Kensuke Yamamoto ,  Kei Shiraishi ,  Kazuhiko Satou ,  Ryo Fukuda ,  Masaru Koyanagi

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.

公开(公告)号：US11568935B2

公开(公告)日：2023-01-31

申请号：US17329317

申请日：2021-05-25

Applicant: Kioxia Corporation

Inventor： Kazuhiko Satou ,  Ryo Fukuda ,  Masaru Koyanagi ,  Kensuke Yamamoto ,  Masato Dome ,  Kei Shiraishi ,  Junya Matsuno ,  Kenro Kubota

IPC: G11C7/00 ,  G11C16/04 ,  G11C16/26 ,  H03K19/00 ,  H03K19/20

Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.