公开(公告)号：US11942431B2

公开(公告)日：2024-03-26

申请号：US17874565

申请日：2022-07-27

Applicant: KIOXIA CORPORATION

Inventor： Nobuyuki Momo ,  Keisuke Nakatsuka

IPC: H01L23/538 ,  H01L23/482 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L27/07 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L23/5386 ,  H01L23/4821 ,  H01L23/5223 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0733 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/0603 ,  H01L2224/8034 ,  H01L2924/1205 ,  H01L2924/19041

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

公开(公告)号：US11688726B2

公开(公告)日：2023-06-27

申请号：US17189955

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Yasunori Iwashita ,  Shinya Arai ,  Keisuke Nakatsuka ,  Takahiro Tomimatsu ,  Ryo Tanaka

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/06 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/06151 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/8234 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.

公开(公告)号：US11437324B2

公开(公告)日：2022-09-06

申请号：US16807835

申请日：2020-03-03

Applicant: KIOXIA CORPORATION

Inventor： Nobuyuki Momo ,  Keisuke Nakatsuka

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/482 ,  H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L27/08 ,  H01L27/07

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

公开(公告)号：US11422712B2

公开(公告)日：2022-08-23

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

公开(公告)号：US11276700B2

公开(公告)日：2022-03-15

申请号：US16559363

申请日：2019-09-03

Applicant: KIOXIA CORPORATION

Inventor： Keisuke Nakatsuka

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/8229 ,  H01L27/11514 ,  H01L21/822 ,  G11C16/04

Abstract: A semiconductor memory device includes first conductive layers stacked on a substrate; second conductive layers stacked on the substrate and apart from the first conductive layer in a direction; third conductive layers stacked on the substrate and electrically connected to the first and second conductive layers; first insulating layers arranged in the direction to sandwich the first conductive layers; second insulating layers arranged in the direction to sandwich the second conductive layers; slit regions that sandwich the third conductive layers; and memory pillars disposed on the first and second insulating layers. The slit region is disposed between an end portion of one of the first insulating layers and an end portion of one of the second insulating layers.

公开(公告)号：US12232325B2

公开(公告)日：2025-02-18

申请号：US17462854

申请日：2021-08-31

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Yoshitaka Kubota ,  Tetsuaki Utsumi ,  Yoshiro Shimojo ,  Ryota Katsumata

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

公开(公告)号：US11574663B2

公开(公告)日：2023-02-07

申请号：US17109853

申请日：2020-12-02

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Tomoya Sanuki ,  Takashi Maeda ,  Go Shikata ,  Hideaki Aochi

IPC: G11C7/10 ,  G11C7/08 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  G11C7/18

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US11411016B2

公开(公告)日：2022-08-09

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Hiroshi Maejima ,  Kenichiro Yoshii ,  Takashi Maeda ,  Hideo Wada

IPC: H01L27/11565 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11578 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11563 ,  H01L27/11568

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.

公开(公告)号：US11289505B2

公开(公告)日：2022-03-29

申请号：US16801336

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Naoya Yoshimura ,  Keisuke Nakatsuka

IPC: H01L27/11582 ,  G11C7/18 ,  G11C8/14 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view.

公开(公告)号：US11984394B2

公开(公告)日：2024-05-14

申请号：US17438728

申请日：2019-03-19

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Yasuhito Yoshimizu ,  Tomoya Sanuki ,  Fumitaka Arai

IPC: H10B41/27 ,  H01L23/522 ,  H01L23/535 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.