公开(公告)号：US11915759B2

公开(公告)日：2024-02-27

申请号：US17556663

申请日：2021-12-20

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/12 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US11238936B2

公开(公告)日：2022-02-01

申请号：US17014677

申请日：2020-09-08

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/12 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US11264102B2

公开(公告)日：2022-03-01

申请号：US17007896

申请日：2020-08-31

Applicant: Kioxia Corporation

Inventor： Kiichi Tachi ,  Takashi Hirotani

IPC: G11C16/06 ,  G11C16/24 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

Abstract: A semiconductor storage device includes a bit line driver, and a control circuit configured to be able to execute a writing sequence for repeating at least one loop including a program operation for writing data into at least one of the plurality of memory cells and a verify operation for verifying the data a plurality of times while increasing a program voltage by a step-up voltage. The bit line driver can obtain a number of memory cells into which writing is completed or a number of memory cells into which writing is insufficient for each of the at least two consecutive loops from a result of the verify operation, and the control circuit can determine the step-up voltage in the subsequent loop based on a result obtained by the bit line driver.

公开(公告)号：US12283544B2

公开(公告)日：2025-04-22

申请号：US17403678

申请日：2021-08-16

Applicant: KIOXIA CORPORATION

Inventor： Kiichi Tachi

IPC: H01L23/528 ,  H10B43/27

Abstract: A semiconductor storage device includes a first stacked region, a second stacked region, and a connection region arranged between the first and second stacked regions. In the connection region, one of a plurality of conductor layers in an upper stepped portion is connected to one of the plurality of conductor layers in the first stacked region via one of the plurality of conductor layers in a bridge portion.

公开(公告)号：US20220115070A1

公开(公告)日：2022-04-14

申请号：US17556663

申请日：2021-12-20

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/12 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.