公开(公告)号：USRE49274E1

公开(公告)日：2022-11-01

申请号：US16284203

申请日：2019-02-25

Applicant: KIOXIA CORPORATION

Inventor： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

IPC: G11C16/04 ,  G11C16/24

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

公开(公告)号：USRE50025E1

公开(公告)日：2024-06-25

申请号：US17004584

申请日：2020-08-27

Applicant: Kioxia Corporation

Inventor： Koji Hosono

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3418 ,  G11C2211/565

Abstract: A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.

公开(公告)号：US11295823B2

公开(公告)日：2022-04-05

申请号：US16909418

申请日：2020-06-23

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C7/10 ,  G11C16/34 ,  G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06 ,  G06F12/02 ,  G11C16/06 ,  G11C16/08

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.