公开(公告)号：US11462556B2

公开(公告)日：2022-10-04

申请号：US17071332

申请日：2020-10-15

Applicant: Kioxia Corporation

Inventor： Tetsuya Furukawa ,  Tomoaki Shino ,  Mitsuhiro Noguchi ,  Shinichi Watanabe ,  Yukio Nishida ,  Hiroyasu Tanaka

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.

公开(公告)号：US11756898B2

公开(公告)日：2023-09-12

申请号：US17120341

申请日：2020-12-14

Applicant: KIOXIA CORPORATION

Inventor： Hideki Itai ,  Mitsuhiro Noguchi ,  Hiromasa Yoshimori ,  Hideyuki Tabata ,  Yasushi Nakajima

IPC: H01L27/11582 ,  H01L23/00 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure.

公开(公告)号：US11239317B2

公开(公告)日：2022-02-01

申请号：US16807230

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Shoichi Watanabe ,  Mitsuhiro Noguchi

IPC: H01L29/08 ,  H01L27/092 ,  H01L27/11573 ,  H01L29/34 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/11582 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11578 ,  G11C16/30

Abstract: According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WT2 disposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.

公开(公告)号：USRE49274E1

公开(公告)日：2022-11-01

申请号：US16284203

申请日：2019-02-25

Applicant: KIOXIA CORPORATION

Inventor： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

IPC: G11C16/04 ,  G11C16/24

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

公开(公告)号：US11227915B2

公开(公告)日：2022-01-18

申请号：US16996491

申请日：2020-08-18

Applicant: KIOXIA CORPORATION

Inventor： Ryuta Tezuka ,  Mitsuhiro Noguchi ,  Tomoaki Shino

IPC: H01L29/06 ,  H01L23/00 ,  H01L25/18

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.

公开(公告)号：US11574994B2

公开(公告)日：2023-02-07

申请号：US17211035

申请日：2021-03-24

Applicant: Kioxia Corporation

Inventor： Masahiro Shimura ,  Mitsuhiro Noguchi

IPC: H01L49/02 ,  H01L27/06 ,  H01L23/522

Abstract: A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.

公开(公告)号：US11251122B2

公开(公告)日：2022-02-15

申请号：US16984208

申请日：2020-08-04

Applicant: Kioxia Corporation

Inventor： Masayuki Akou ,  Mitsuhiro Noguchi ,  Yuuichi Tatsumi

IPC: H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(π/4).