公开(公告)号：US11889699B2

公开(公告)日：2024-01-30

申请号：US18100615

申请日：2023-01-24

申请人： Kioxia Corporation

发明人： Naohito Morozumi ,  Hiroshi Maejima

IPC分类号： H10B43/40 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00 ,  G11C7/06 ,  H10B43/10 ,  H10B43/35 ,  G11C5/02

CPC分类号： H10B43/40 ,  G11C5/025 ,  G11C7/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  H01L24/05 ,  H01L24/20 ,  H10B43/10 ,  H10B43/35 ,  H01L2924/1438

摘要： A semiconductor memory device including a substrate having a first region and a second region; a plurality of first transistors provided in the first region; a plurality of second transistors provided in the second region, the plurality of second transistors being electrically coupled to the plurality of first transistors, respectively, and a breakdown-voltage of the second transistor being lower than a breakdown-voltage of the first transistor. A plurality of joint metals are provided above the first region, the plurality of joint metals being electrically coupled to the plurality of first transistors, respectively. A plurality of bit lines are provided in an upper layer of the plurality of joint metals, the plurality of bit lines being coupled to the plurality of joint metals, respectively; and a plurality of memory cells are provided in an upper layer of the plurality of bit lines, the plurality of memory cells being coupled to the plurality of bit lines, respectively.

公开(公告)号：US11594546B2

公开(公告)日：2023-02-28

申请号：US16795763

申请日：2020-02-20

申请人： KIOXIA CORPORATION

发明人： Naohito Morozumi ,  Hiroshi Maejima

IPC分类号： H01L27/1157 ,  G11C16/16 ,  H01L27/11573 ,  H01L27/11565 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00 ,  G11C7/06

摘要： A semiconductor memory device according to an embodiment includes a memory chip and a circuit chip. The memory chip includes first and second joint metals. The circuit chip includes first and second sense amplifiers, and third and fourth joint metals facing the first and second joint metals, respectively. The first sense amplifier includes first and second active regions. The first active region includes a first transistor coupled between the third joint metal and the second active region. The second amplifier includes third and fourth active region. The third active region includes a second transistor coupled between the fourth joint metal and the fourth active region. The third and fourth joint metals overlap the first and third active regions, respectively.