公开(公告)号：US20240295969A1

公开(公告)日：2024-09-05

申请号：US18592763

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

公开(公告)号：US20230342051A1

公开(公告)日：2023-10-26

申请号：US18343835

申请日：2023-06-29

Applicant: KIOXIA CORPORATION

Inventor： Shunichi IGAHARA ,  Toshikatsu HIDA ,  Riki SUZUKI ,  Takehiko AMAKI ,  Suguru NISHIKAWA ,  Yoshihisa KOJIMA

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US20230073249A1

公开(公告)日：2023-03-09

申请号：US17685229

申请日：2022-03-02

Applicant: KIOXIA CORPORATION

Inventor： Suguru NISHIKAWA ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Takehiko AMAKI

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

公开(公告)号：US20220300190A1

公开(公告)日：2022-09-22

申请号：US17468895

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Riki SUZUKI

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

公开(公告)号：US20220058085A1

公开(公告)日：2022-02-24

申请号：US17519356

申请日：2021-11-04

Applicant: KIOXIA CORPORATION

Inventor： Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.

公开(公告)号：US20210257027A1

公开(公告)日：2021-08-19

申请号：US17018147

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Shunichi IGAHARA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US20240385760A1

公开(公告)日：2024-11-21

申请号：US18788695

申请日：2024-07-30

Applicant: KIOXIA CORPORATION

Inventor： Shunichi IGAHARA ,  Toshikatsu HIDA ,  Riki SUZUKI ,  Takehiro AMAKI ,  Suguru NISHIKAWA ,  Yoshihisa KOJIMA

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US20220300185A1

公开(公告)日：2022-09-22

申请号：US17447088

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

IPC: G06F3/06

Abstract: According to one embodiment, a storage device comprises a nonvolatile memory, and a controller configured to perform a first data write operation in a first mode, and to perform a second data write operation in a second mode. Data of a first number of bits is written per memory cell in the first mode. Data of a second number of bits is written per memory cell in the second mode. The second number is larger than the first number. The controller reserves one or more free blocks as write destination block candidates of the first data write operation, perform the first data write operation for one of the write destination block candidates, and perform a garbage collection.

公开(公告)号：US20220261174A1

公开(公告)日：2022-08-18

申请号：US17368587

申请日：2021-07-06

Applicant: Kioxia Corporation

Inventor： Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile memory, and a memory controller. The memory controller receives a write request for data, and determines a unit of a logical-to-physical address conversion which is a conversion between a logical address associated with the data and a physical address of the non-volatile memory into which the data is to be written, according to a size of the data.

公开(公告)号：US20220130462A1

公开(公告)日：2022-04-28

申请号：US17572279

申请日：2022-01-10

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Shunichi IGAHARA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.