公开(公告)号：US20240420778A1

公开(公告)日：2024-12-19

申请号：US18815516

申请日：2024-08-26

Applicant: Kioxia Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Kengo KUROSE ,  Marie TAKADA ,  Ryo YAMAKI ,  Kiyotaka IWASAKI ,  Yoshihisa KOJIMA

IPC: G11C16/26 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C29/52 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

公开(公告)号：US20240176490A1

公开(公告)日：2024-05-30

申请号：US18431159

申请日：2024-02-02

Applicant: KIOXIA CORPORATION

Inventor： Yoshihisa KOJIMA ,  Masanobu SHIRAKAWA ,  Kiyotaka IWASAKI

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

公开(公告)号：US20230420060A1

公开(公告)日：2023-12-28

申请号：US18459501

申请日：2023-09-01

Applicant: KIOXIA CORPORATION

Inventor： Tomoya KAMATA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

IPC: G11C16/32 ,  G11C7/22

CPC classification number: G11C16/32 ,  G11C7/22

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.

公开(公告)号：US20230139665A1

公开(公告)日：2023-05-04

申请号：US18092158

申请日：2022-12-30

Applicant: Kioxia Corporation

Inventor： Marie SIA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA ,  Riki SUZUKI

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

公开(公告)号：US20230096401A1

公开(公告)日：2023-03-30

申请号：US17694057

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Masahiro KIYOOKA ,  Riki SUZUKI ,  Yoshihisa KOJIMA

IPC: H03M13/11 ,  H03M13/09 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

公开(公告)号：US20210295921A1

公开(公告)日：2021-09-23

申请号：US17184991

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Riki SUZUKI ,  Yoshihisa KOJIMA

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/22 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

公开(公告)号：US20240295969A1

公开(公告)日：2024-09-05

申请号：US18592763

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

公开(公告)号：US20240021252A1

公开(公告)日：2024-01-18

申请号：US18365929

申请日：2023-08-04

Applicant: Kioxia Corporation

Inventor： Yoshihisa KOJIMA

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  G11C7/04 ,  G11C16/10

CPC classification number: G11C16/32 ,  G11C16/26 ,  G11C16/08 ,  G11C11/5628 ,  G11C16/3495 ,  G11C16/0483 ,  G11C7/04 ,  G11C16/10 ,  G11C2211/5648

Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

公开(公告)号：US20230402100A1

公开(公告)日：2023-12-14

申请号：US18455575

申请日：2023-08-24

Applicant: KIOXIA CORPORATION

Inventor： Riki SUZUKI ,  Yoshihisa KOJIMA

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/44 ,  G11C16/22 ,  G11C7/10 ,  G11C29/42 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/44 ,  G11C16/22 ,  G11C7/1045 ,  G11C29/42 ,  G11C16/30

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

公开(公告)号：US20230342051A1

公开(公告)日：2023-10-26

申请号：US18343835

申请日：2023-06-29

Applicant: KIOXIA CORPORATION

Inventor： Shunichi IGAHARA ,  Toshikatsu HIDA ,  Riki SUZUKI ,  Takehiko AMAKI ,  Suguru NISHIKAWA ,  Yoshihisa KOJIMA

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.