公开(公告)号：US20230275601A1

公开(公告)日：2023-08-31

申请号：US18312834

申请日：2023-05-05

Applicant: KIOXIA CORPORATION

Inventor： Riki SUZUKI ,  Toshikatsu HIDA ,  Osamu TORII ,  Hiroshi YAO ,  Kiyotaka IWASAKI

IPC: H03M13/35 ,  G06F11/10 ,  H03M13/29 ,  G06F3/06 ,  G11C29/52

CPC classification number: H03M13/35 ,  G06F11/1044 ,  G06F11/1008 ,  G06F11/1076 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/2906 ,  G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G11C29/52 ,  G11C7/1006

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

公开(公告)号：US20220300190A1

公开(公告)日：2022-09-22

申请号：US17468895

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Riki SUZUKI

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

公开(公告)号：US20200303012A1

公开(公告)日：2020-09-24

申请号：US16799885

申请日：2020-02-25

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Riki SUZUKI ,  Yoshihisa KOJIMA

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/12 ,  G11C16/34 ,  G06F13/16

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

公开(公告)号：US20230139665A1

公开(公告)日：2023-05-04

申请号：US18092158

申请日：2022-12-30

Applicant: Kioxia Corporation

Inventor： Marie SIA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA ,  Riki SUZUKI

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

公开(公告)号：US20230096401A1

公开(公告)日：2023-03-30

申请号：US17694057

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Masahiro KIYOOKA ,  Riki SUZUKI ,  Yoshihisa KOJIMA

IPC: H03M13/11 ,  H03M13/09 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

公开(公告)号：US20210295921A1

公开(公告)日：2021-09-23

申请号：US17184991

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Riki SUZUKI ,  Yoshihisa KOJIMA

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/22 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

公开(公告)号：US20240320097A1

公开(公告)日：2024-09-26

申请号：US18590217

申请日：2024-02-28

Applicant: Kioxia Corporation

Inventor： Riki SUZUKI ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

IPC: G06F11/14 ,  G06F11/10

CPC classification number: G06F11/141 ,  G06F11/1048 ,  G06F11/1068

Abstract: A memory system includes a nonvolatile memory; and a controller configured to (i) select one of a plurality of read retry processes having different average required times, respectively, based on reliability of a target area of the nonvolatile memory on which a read process is to be executed and (ii) execute the selected read retry process.

公开(公告)号：US20230320087A1

公开(公告)日：2023-10-05

申请号：US18314527

申请日：2023-05-09

Applicant: KIOXIA CORPORATION

Inventor： Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Toshikatsu HIDA ,  Marie Grace Izabelle Angeles SIA ,  Riki SUZUKI ,  Shohei ASAMI

IPC: H10B41/27 ,  G11C16/08 ,  G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C7/04 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

公开(公告)号：US20230207016A1

公开(公告)日：2023-06-29

申请号：US18117520

申请日：2023-03-06

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Yoshihisa KOJIMA ,  Riki SUZUKI ,  Masanobu SHIRAKAWA ,  Toshikatsu HIDA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/14 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/0659 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/3495 ,  G11C29/028 ,  G11C16/349 ,  G11C29/42 ,  G11C16/3459 ,  G11C29/021 ,  G11C16/32 ,  G11C11/5671 ,  H10B43/27

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

公开(公告)号：US20220328102A1

公开(公告)日：2022-10-13

申请号：US17849062

申请日：2022-06-24

Applicant: KIOXIA CORPORATION

Inventor： Suguru NISHIKAWA ,  Yoshihisa KOJIMA ,  Riki SUZUKI ,  Masanobu SHIRAKAWA ,  Toshikatsu HIDA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.