公开(公告)号：US20210295941A1

公开(公告)日：2021-09-23

申请号：US17022274

申请日：2020-09-16

Applicant: Kioxia Corporation

Inventor： Shohei ASAMI ,  Takehiko AMAKI

IPC: G11C29/42 ,  G11C16/10 ,  G11C16/04 ,  G11C29/44 ,  G11C29/50 ,  G11C29/12 ,  G11C16/26

Abstract: According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.

公开(公告)号：US20240295969A1

公开(公告)日：2024-09-05

申请号：US18592763

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

公开(公告)号：US20230342051A1

公开(公告)日：2023-10-26

申请号：US18343835

申请日：2023-06-29

Applicant: KIOXIA CORPORATION

Inventor： Shunichi IGAHARA ,  Toshikatsu HIDA ,  Riki SUZUKI ,  Takehiko AMAKI ,  Suguru NISHIKAWA ,  Yoshihisa KOJIMA

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US20210081276A1

公开(公告)日：2021-03-18

申请号：US16806131

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Riki SUZUKI ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

公开(公告)号：US20240284668A1

公开(公告)日：2024-08-22

申请号：US18653241

申请日：2024-05-02

Applicant: KIOXIA CORPORATION

Inventor： Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Toshikatsu HIDA ,  Marie Grace Izabelle Angeles SIA ,  Riki SUZUKI ,  Shohei ASAMI

IPC: H10B41/27 ,  G11C7/04 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

公开(公告)号：US20220300185A1

公开(公告)日：2022-09-22

申请号：US17447088

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

IPC: G06F3/06

Abstract: According to one embodiment, a storage device comprises a nonvolatile memory, and a controller configured to perform a first data write operation in a first mode, and to perform a second data write operation in a second mode. Data of a first number of bits is written per memory cell in the first mode. Data of a second number of bits is written per memory cell in the second mode. The second number is larger than the first number. The controller reserves one or more free blocks as write destination block candidates of the first data write operation, perform the first data write operation for one of the write destination block candidates, and perform a garbage collection.

公开(公告)号：US20220261174A1

公开(公告)日：2022-08-18

申请号：US17368587

申请日：2021-07-06

Applicant: Kioxia Corporation

Inventor： Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile memory, and a memory controller. The memory controller receives a write request for data, and determines a unit of a logical-to-physical address conversion which is a conversion between a logical address associated with the data and a physical address of the non-volatile memory into which the data is to be written, according to a size of the data.

公开(公告)号：US20220130462A1

公开(公告)日：2022-04-28

申请号：US17572279

申请日：2022-01-10

Applicant: Kioxia Corporation

Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Yoshihisa KOJIMA ,  Shunichi IGAHARA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

公开(公告)号：US20210286671A1

公开(公告)日：2021-09-16

申请号：US17198451

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Takehiko AMAKI ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0891

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

公开(公告)号：US20210073119A1

公开(公告)日：2021-03-11

申请号：US16807275

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Takehiko AMAKI ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

IPC: G06F12/02 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.