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公开(公告)号：US20230139665A1
公开(公告)日：2023-05-04
申请号：US18092158
申请日：2022-12-30
申请人： Kioxia Corporation
发明人： Marie SIA , Yoshihisa KOJIMA , Suguru NISHIKAWA , Riki SUZUKI
摘要： A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.
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公开(公告)号：US20210081276A1
公开(公告)日：2021-03-18
申请号：US16806131
申请日：2020-03-02
申请人： KIOXIA CORPORATION
摘要： A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.
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公开(公告)号：US20220261174A1
公开(公告)日：2022-08-18
申请号：US17368587
申请日：2021-07-06
申请人： Kioxia Corporation
IPC分类号： G06F3/06
摘要： According to one embodiment, a memory system includes a non-volatile memory, and a memory controller. The memory controller receives a write request for data, and determines a unit of a logical-to-physical address conversion which is a conversion between a logical address associated with the data and a physical address of the non-volatile memory into which the data is to be written, according to a size of the data.
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公开(公告)号：US20220130462A1
公开(公告)日：2022-04-28
申请号：US17572279
申请日：2022-01-10
申请人： Kioxia Corporation
摘要： According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
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公开(公告)号：US20210286671A1
公开(公告)日：2021-09-16
申请号：US17198451
申请日：2021-03-11
申请人： Kioxia Corporation
IPC分类号： G06F11/10 , G06F11/07 , G06F12/02 , G06F12/0891
摘要： According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.
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公开(公告)号：US20210073119A1
公开(公告)日：2021-03-11
申请号：US16807275
申请日：2020-03-03
申请人： Kioxia Corporation
摘要： According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.
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公开(公告)号：US20230073249A1
公开(公告)日：2023-03-09
申请号：US17685229
申请日：2022-03-02
申请人： KIOXIA CORPORATION
IPC分类号： G06F3/06
摘要： According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.
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公开(公告)号：US20220058085A1
公开(公告)日：2022-02-24
申请号：US17519356
申请日：2021-11-04
申请人： KIOXIA CORPORATION
摘要： A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.
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公开(公告)号：US20210257027A1
公开(公告)日：2021-08-19
申请号：US17018147
申请日：2020-09-11
申请人： Kioxia Corporation
摘要： According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
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公开(公告)号：US20210124529A1
公开(公告)日：2021-04-29
申请号：US17002173
申请日：2020-08-25
申请人： Kioxia Corporation
摘要： A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.
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