公开(公告)号：US20240055363A1

公开(公告)日：2024-02-15

申请号：US18446236

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Susumu YAMAMOTO ,  Hideki MATSUSHIGE ,  Gen TOYOTA

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L24/08 ,  H01L24/06 ,  H01L23/481 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2223/54426 ,  H01L2224/06515 ,  H01L2224/0603 ,  H01L2224/8013

Abstract: There is provided a semiconductor device including a first chip and a second chip bonded to the first chip. The first chip includes a first alignment mark provided in a first region of a bonding surface and a plurality of first dummy pads provided in a second region of the bonding surface different from the first region. The second chip includes a second alignment mark provided on the bonding surface corresponding to the first alignment mark and a plurality of second dummy pads provided in a region of the bonding surface different from the second alignment mark. A coverage of the first alignment mark in the first region is substantially the same as the coverage of the first dummy pads in the second region.

公开(公告)号：US20220013477A1

公开(公告)日：2022-01-13

申请号：US17189718

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Soichi HOMMA ,  Tatsuo MIGITA ,  Masayuki MIURA ,  Takeori MAEDA ,  Kazuhiro KATO ,  Susumu YAMAMOTO

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

公开(公告)号：US20230411287A1

公开(公告)日：2023-12-21

申请号：US18178346

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Eiichi SHIN ,  Satoshi HONGO ,  Susumu YAMAMOTO ,  Yukio KATAMURA ,  Gen TOYOTA ,  Tsutomu FUJITA

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/20 ,  H10B43/35 ,  H10B41/35 ,  H10B41/20

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/20 ,  H10B43/35 ,  H10B41/35 ,  H10B41/20

Abstract: A semiconductor device includes a wiring layer; a first stacked body disposed on the wiring layer; a second stacked body disposed on the first stacked body in a stacking direction; and a first resin body disposed around a periphery of the first stacked body. The first stacked body includes a first pad electrically connected to the wiring layer, a first device layer electrically connected to the first pad, and a first electrode electrically connected to the first device layer. The second stacked body includes a second pad electrically connected to the first electrode and a second device layer electrically connected to the second pad. In the stacking direction, the first resin body is vertically located closer to the wiring layer than an interface between the first stacked body and the second stacked body.

公开(公告)号：US20230101002A1

公开(公告)日：2023-03-30

申请号：US17694080

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Gen TOYOTA ,  Satoshi HONGO ,  Tatsuo MIGITA ,  Susumu YAMAMOTO ,  Tsutomu FUJITA ,  Eiichi SHIN ,  Yukio KATAMURA ,  Hideki MATSUSHIGE ,  Kazuki TAKAHASHI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.

公开(公告)号：US20220375901A1

公开(公告)日：2022-11-24

申请号：US17682925

申请日：2022-02-28

Applicant: KIOXIA CORPORATION

Inventor： Susumu YAMAMOTO ,  Tsutomu FUJITA ,  Takeori MAEDA ,  Satoshi HONGO ,  Gen TOYOTA ,  Eiichi SHIN ,  Yukio KATAMURA

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies includes a plurality of semiconductor chips. The method further includes forming a plurality of first wires on the stacked bodies. The first wires connecting the stacked bodies to each other. The method further includes forming a resin layer on the stacked bodies and the first wires, then thinning he resin layer until the first wires are exposed.