公开(公告)号：US20240090221A1

公开(公告)日：2024-03-14

申请号：US18459697

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Yoichi MINEMURA

IPC: H10B43/27

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: A memory device includes: insulator layers spaced apart from one another in a first direction; conductor layers spaced apart from one another in the first direction, the insulator layers and the insulator layers alternately arranged along the first direction; and a memory pillar extending in the first direction to intersect the conductor layers. The conductor layers include a first conductor layer having a first portion and a second portion in contact with the memory pillar. The first portion is recessed relative to the second portion in a second direction intersecting the first direction.

公开(公告)号：US20240321359A1

公开(公告)日：2024-09-26

申请号：US18593980

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Yoichi MINEMURA

IPC: G11C16/04 ,  G11C16/10 ,  H10B43/27

CPC classification number: G11C16/0483 ,  G11C16/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a stacked body in which conductive layers are stacked with an insulating layer interposed therebetween, a semiconductor film to provide a channel for a plurality of memory cell transistors having gates electrically connected to the conductive layers of the stacked body, respectively, an insulating film extending in the stacking direction between the conductive layers and the semiconductor film, and a control circuit configured to control a program voltage to be applied to a conductive layer electrically connected to a memory cell transistor that is a target of a write operation, and a transfer voltage to be applied to conductive layers electrically connected to other memory cell transistors that are not the target of the write operation, wherein the control circuit is configured to vary the transfer voltage to be applied depending on a number of bits that are being written in the write operation.

公开(公告)号：US20230282290A1

公开(公告)日：2023-09-07

申请号：US17900288

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Yoichi MINEMURA

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/0483

Abstract: A semiconductor storage device includes a first word line, a first insulating layer extending along the first word line, a first memory cell connected to the first word line, a second memory cell connected to the first word line, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, and a control circuit. The second memory cell is farther from the first insulating layer than the first memory cell. The control circuit is configured to apply a first voltage to the first bit line during a read operation of the first memory cell, and apply a second voltage to the second bit line during a read operation of the second memory cell. The second voltage is higher than the first voltage.

公开(公告)号：US20210280256A1

公开(公告)日：2021-09-09

申请号：US16993509

申请日：2020-08-14

Applicant: Kioxia Corporation

Inventor： Kazuharu YAMABE ,  Yoichi MINEMURA

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.

公开(公告)号：US20230065666A1

公开(公告)日：2023-03-02

申请号：US17684076

申请日：2022-03-01

Applicant: KIOXIA CORPORATION

Inventor： Yoichi MINEMURA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: According to one embodiment, a semiconductor memory device includes first conductive layers stacked on a substrate at a first pitch, second conductive layers stacked on the substrate at a second pitch, and third conductive layers stacked on the substrate at a third pitch. The third conductive layers are between the substrate and the second conductive layers in a first direction. A semiconductor layer extends in the first direction through the first conductive layers, the second conductive layers, and the third conductive layers. The semiconductor layer has a first portion facing the first conductive layers and the second conductive layers and a second portion facing the third conductive layers. The second pitch is greater than the first pitch and the third pitch.

公开(公告)号：US20210296352A1

公开(公告)日：2021-09-23

申请号：US17004777

申请日：2020-08-27

Applicant: KIOXIA CORPORATION

Inventor： Yoichi MINEMURA ,  Kensei TAKAHASHI ,  Takashi ASANO

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor storage device includes first and second stacked bodies, a first semiconductor layer, a first charge storage layer, a conductive layer, and a first silicon oxide layer. The first stacked body includes first insulation layers and first gate electrode layers that are alternately stacked in a first direction. The first semiconductor layer extends in the first stacked body in the first direction. The first charge storage layer is provided between the first semiconductor layer and the first gate electrode layers. The conductive layer is provided between the first stacked body and the second stacked body and extends in the first direction and a second direction. The first silicon oxide layer is provided between the conductive layer and the first gate electrode layers. The first silicon oxide layer containing an impurity being at least one of phosphorus, boron, carbon, and fluorine.