公开(公告)号：US20050048763A1

公开(公告)日：2005-03-03

申请号：US10727966

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Yan-Hong Chen ,  Yi-Nan Chen ,  Chang-Rong Wu

发明人： Kaan-Lu Tzou ,  Yan-Hong Chen ,  Yi-Nan Chen ,  Chang-Rong Wu

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02129 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76829

摘要： A method of forming an interlayer dielectric (ILD) layer. A dielectric layer containing boron and phosphorous is formed overlying a substrate. A plasma treatment is subsequently performed on the dielectric layer using argon or nitrogen as a process gas. A capping layer is formed in-situ overlying the dielectric layer to serve as the ILD layer with the dielectric layer. A reflow process is subsequently performed on the ILD layer. A method for preventing formation of etching defects in a contact is also disclosed.

公开(公告)号：US06900118B2

公开(公告)日：2005-05-31

申请号：US10727966

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Yan-Hong Chen ,  Yi-Nan Chen ,  Chang-Rong Wu

发明人： Kaan-Lu Tzou ,  Yan-Hong Chen ,  Yi-Nan Chen ,  Chang-Rong Wu

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/02129 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76829

摘要： A method of forming an interlayer dielectric (ILD) layer. A dielectric layer containing boron and phosphorous is formed overlying a substrate. A plasma treatment is subsequently performed on the dielectric layer using argon or nitrogen as a process gas. A capping layer is formed in-situ overlying the dielectric layer to serve as the ILD layer with the dielectric layer. A reflow process is subsequently performed on the ILD layer. A method for preventing formation of etching defects in a contact is also disclosed.

摘要翻译： 一种形成层间电介质（ILD）层的方法。 在衬底上形成含有硼和磷的电介质层。 随后使用氩或氮作为工艺气体在电介质层上进行等离子体处理。 在介质层上原位形成覆盖层，作为具有电介质层的ILD层。 随后在ILD层上进行回流处理。 还公开了防止接触中的蚀刻缺陷形成的方法。

公开(公告)号：US20060127680A1

公开(公告)日：2006-06-15

申请号：US11348626

申请日：2006-02-07

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： B32B17/06 ,  B32B9/00

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

公开(公告)号：US07029753B2

公开(公告)日：2006-04-18

申请号：US10727790

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： B23B17/06

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US20050042871A1

公开(公告)日：2005-02-24

申请号：US10727790

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： C03C15/00 ,  H01L21/033 ,  H01L21/308 ,  H01L21/8242 ,  B32B17/06 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US07341952B2

公开(公告)日：2008-03-11

申请号：US11348626

申请日：2006-02-07

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L21/302

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US06727159B2

公开(公告)日：2004-04-27

申请号：US10163239

申请日：2002-06-04

申请人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Kaan-Lu Tzou

发明人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Kaan-Lu Tzou

IPC分类号： H01L2176

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76224

摘要： A method of forming a shallow trench isolation in a semiconductor substrate. First, a hard mask consisting of a pad nitride and a pad oxide is formed on the semiconductor substrate. The semiconductor substrate is anisotrpically etched to form a trench while the hard mask is used as the etching mask. A thermal oxide film is grown on the trench. Then, a nitride liner is formed on the thermal oxide film. Next, a silicon rich oxide layer is conformally deposited on the nitride liner by high density plasma chemical vapor deposition without a bias voltage applied to the semiconductor substrate. Then, a silicon oxide is deposited to fill the trench by high density plasma chemical vapor deposition while a bias voltage is applied to the semiconductor substrate.

摘要翻译： 一种在半导体衬底中形成浅沟槽隔离的方法。 首先，在半导体基板上形成由衬垫氮化物和衬垫氧化物构成的硬掩模。 在使用硬掩模作为蚀刻掩模的情况下，各向异性蚀刻半导体衬底以形成沟槽。 在沟槽上生长热氧化膜。 然后，在热氧化膜上形成氮化物衬垫。 接下来，通过高密度等离子体化学气相沉积在氮化物衬垫上共形沉积富硅氧化物层，而不施加施加到半导体衬底的偏置电压。 然后，沉积氧化硅以通过高密度等离子体化学气相沉积来填充沟槽，同时向半导体衬底施加偏置电压。