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1.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming 失效需要双极性编程的双极型二极管三维存储器的解码方案公开(公告)号：US08755213B2
公开(公告)日：2014-06-17
申请号：US13407848
申请日：2012-02-29
CPC分类号： G11C13/0069 , G11C5/025 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C2013/0071 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
摘要翻译： 一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。 该系统包括列电压。 列电压开关包括列电压和电耦合到双向存取二极管的输出。 列电压包括至少一个写一列电压和至少一个写零列电压。 该系统还包括行电压开关。 行电压开关包括行电压和电耦合到双向存取二极管的输出。 行电压包括至少一个写入一行电压和至少一个写入零行电压。 该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。 该系统包括电耦合到行和列开关的选择线的写入驱动器。
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2.发明申请DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING BIPOLAR PROGRAMMING 失效用于双极二极管的解码方案三维存储器需要双极性编程公开(公告)号：US20130223125A1
公开(公告)日：2013-08-29
申请号：US13407848
申请日：2012-02-29
CPC分类号： G11C13/0069 , G11C5/025 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C2013/0071 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
摘要翻译： 一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。 该系统包括列电压。 列电压开关包括列电压和电耦合到双向存取二极管的输出。 列电压包括至少一个写一列电压和至少一个写零列电压。 该系统还包括行电压开关。 行电压开关包括行电压和电耦合到双向存取二极管的输出。 行电压包括至少一个写入一行电压和至少一个写入零行电压。 该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。 该系统包括电耦合到行和列开关的选择线的写入驱动器。
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3.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权需要单极编程的双极型二极管三维存储器的解码方案公开(公告)号：US08842491B2
公开(公告)日：2014-09-23
申请号：US13551597
申请日：2012-07-17
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 该系统包括电耦合到多个列电压的列电压开关。 列电压开关包括电耦合到双向存取二极管的输出。 多个列电压包括至少一个选择列电压和一个取消选择列电压。 该系统包括电耦合到多个行电压的行电压开关。 行电压开关包括电耦合到双向存取二极管的输出。 多个行电压包括至少一个选择行电压和一个取消选择行电压。 该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。
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4.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权需要单极编程的双极型二极管三维存储器的解码方案公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。
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公开(公告)号：US20130039110A1
公开(公告)日：2013-02-14
申请号：US13209405
申请日：2011-08-14
申请人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
发明人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
CPC分类号： G11C13/00 , G11C5/02 , G11C7/00 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/224 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
摘要翻译： 用于在两层半导体晶片上制造存储器件的存储器件和方法。 示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。 此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。 另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造 晶圆。
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6.发明申请DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING 有权用于双极二极管的三维存储器的解码方案需要单核编程公开(公告)号：US20140022851A1
公开(公告)日：2014-01-23
申请号：US13584423
申请日：2012-08-13
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。
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公开(公告)号：US08873271B2
公开(公告)日：2014-10-28
申请号：US13209405
申请日：2011-08-14
申请人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
发明人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
CPC分类号： G11C13/00 , G11C5/02 , G11C7/00 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/224 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
摘要翻译： 用于在两层半导体晶片上制造存储器件的存储器件和方法。 示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。 此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。 另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造 晶圆。
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8.发明申请DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING 有权用于双极二极管的三维存储器的解码方案需要单核编程公开(公告)号：US20140022850A1
公开(公告)日：2014-01-23
申请号：US13551597
申请日：2012-07-17
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 该系统包括电耦合到多个列电压的列电压开关。 列电压开关包括电耦合到双向存取二极管的输出。 多个列电压包括至少一个选择列电压和一个取消选择列电压。 该系统包括电耦合到多个行电压的行电压开关。 行电压开关包括电耦合到双向存取二极管的输出。 多个行电压包括至少一个选择行电压和一个取消选择行电压。 该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。
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公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译： 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间，将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。
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公开(公告)号：US20140052900A1
公开(公告)日：2014-02-20
申请号：US13610830
申请日：2012-09-11
申请人： Bing Dai , Chung H. Lam , Jing Li
发明人： Bing Dai , Chung H. Lam , Jing Li
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F1/32 , G06F12/0246
摘要： A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).
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