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1.发明授权公开(公告)号：US07868640B2
公开(公告)日：2011-01-11
申请号：US12061077
申请日：2008-04-02
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译： 一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。 为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。 电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。 可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。 在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。
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2.发明申请公开(公告)号：US20090251167A1
公开(公告)日：2009-10-08
申请号：US12061077
申请日：2008-04-02
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译： 一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。 为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。 电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。 可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。 在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。
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3.发明授权Measurement methodology and array structure for statistical stress and test of reliabilty structures 失效统计应力的测量方法和阵列结构以及可靠性结构的测试公开(公告)号：US08120356B2
公开(公告)日：2012-02-21
申请号：US12482999
申请日：2009-06-11
IPC分类号： G01V3/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译： 在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。 该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛 。 在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。 虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。
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4.发明申请MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES 失效统计应力的测量方法和阵列结构和可靠性结构测试公开(公告)号：US20100318313A1
公开(公告)日：2010-12-16
申请号：US12482999
申请日：2009-06-11
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译： 在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。 该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛 。 在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。 虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。
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5.发明授权Parallel array architecture for constant current electro-migration stress testing 失效用于恒流电迁移应力测试的并行阵列架构公开(公告)号：US08217671B2
公开(公告)日：2012-07-10
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/00
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。
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6.发明申请Parallel Array Architecture for Constant Current Electro-Migration Stress Testing 失效用于恒流电迁移应力测试的并行阵列架构公开(公告)号：US20100327892A1
公开(公告)日：2010-12-30
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。
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7.发明授权Method and test system for fast determination of parameter variation statistics 有权方法和测试系统，用于快速确定参数变化统计公开(公告)号：US08862426B2
公开(公告)日：2014-10-14
申请号：US11961442
申请日：2007-12-20
申请人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
发明人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
IPC分类号： G01R19/00 , G01R31/00 , G01R31/14 , G01R31/28 , G01R31/3185
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/318533 , G01R31/318558
摘要： A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.
摘要翻译： 用于快速确定参数变化统计的方法和测试系统提供了使用低计算能力和容易获得的测试设备来确定过程变化和参数统计的机制。 在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。 阵列的测试输出提供依赖于特定器件参数的电流或电压。 器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。 测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。
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公开(公告)号：US20080284460A1
公开(公告)日：2008-11-20
申请号：US12141862
申请日：2008-06-18
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/36
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。
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9.发明申请公开(公告)号：US20090164155A1
公开(公告)日：2009-06-25
申请号：US11961520
申请日：2007-12-20
申请人： KANAK B. AGARWAL , Jerry D. Hayes , Sani R. Nassif
发明人： KANAK B. AGARWAL , Jerry D. Hayes , Sani R. Nassif
CPC分类号： G01R31/2894 , G01R31/2648 , H01L22/14
摘要： A method and system for isolating dopant fluctuation and device length variation from statistical measurements of threshold voltage provides fast determination of process variation for devices in a characterization array. Statistics of threshold voltage are measured at two different values of drain-source voltage imposed on the devices in the characterization array. At least one moment of the a drain-induced barrier lowering (DIBL) coefficient η, which is a measure of device length and zero-bias threshold voltage VTH0 are computed directly from the statistical moment values of the threshold variation. The standard deviation and mean of η and VTH0 can thereby be obtained having only a statistical description of the threshold voltage for the devices in the array at multiple drain-source voltages. The threshold voltage statistics can be obtained from a digital meter measurement (rms and DC average) of a waveform indicative of threshold voltage produced by sequentially selecting the array devices.
摘要翻译： 从阈值电压的统计测量中分离掺杂剂波动和器件长度变化的方法和系统可以快速确定表征阵列中器件的工艺变化。 在表征阵列中的器件上施加的两个不同的漏源电压值，测量阈值电压的统计。 漏极引起的屏障降低（DIBL）系数eta的至少一个时刻，其是器件长度和零偏置阈值电压VTH0的量度，直接从阈值变化的统计矩值来计算。 因此，可以获得eta和VTH0的标准偏差和平均值，其仅具有在多个漏 - 源电压下阵列中的器件的阈值电压的统计描述。 阈值电压统计可以从表示通过依次选择阵列器件产生的阈值电压的波形的数字计量器测量（均方根和直流平均）获得。
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公开(公告)号：US07397259B1
公开(公告)日：2008-07-08
申请号：US11736146
申请日：2007-04-17
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线进行操作的输入/输出引脚。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。
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