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1.发明申请MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 失效具有多个并联连接的电容器的多端口存储器公开(公告)号：US20070189057A1
公开(公告)日：2007-08-16
申请号：US11306749
申请日：2006-01-10
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译： 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。 这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。 第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。 在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。
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公开(公告)号：US20070080440A1
公开(公告)日：2007-04-12
申请号：US11469039
申请日：2006-08-31
CPC分类号： H01L29/78642 , H01L27/10864 , H01L27/1087
摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。
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公开(公告)号：US20070047293A1
公开(公告)日：2007-03-01
申请号：US11161962
申请日：2005-08-24
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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公开(公告)号：US20060175660A1
公开(公告)日：2006-08-10
申请号：US10906238
申请日：2005-02-10
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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公开(公告)号：US20080102569A1
公开(公告)日：2008-05-01
申请号：US12002828
申请日：2007-12-19
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域 的沟渠 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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6.发明申请SIMPLIFIED BURIED PLATE STRUCTURE AND PROCESS FOR SEMICONDUCTOR-ON-INSULATOR CHIP 有权半导体绝缘子芯片的简化平板结构和工艺公开(公告)号：US20060202249A1
公开(公告)日：2006-09-14
申请号：US10906808
申请日：2005-03-08
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert Ho , Carl Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert Ho , Carl Radens
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/10864 , H01L27/10867 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.
摘要翻译： 本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。 每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单元半导体区域的至少一部分。 掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。 在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。 接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。
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公开(公告)号：US20070222015A1
公开(公告)日：2007-09-27
申请号：US11750423
申请日：2007-05-18
IPC分类号： H01L31/0352
CPC分类号： H01L31/105 , H01L31/03529 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first dopant and having a first thickness slightly greater than one half the width of the narrow trenches, so that the wide trenches have a remaining central aperture; stripping the sacrificial material from the wide trenches in an etch that removes a first thickness, thereby emptying the wide trenches; a) filling the wide trenches with a second sacrificial material of opposite polarity; or b) doping the wide trenches from the ambient such as by gas phase doping, plasma doping, ion implantation, liquid phase doping, infusion doping and plasma immersion ion implantation; diffusing the dopants into the substrate, forming p and n regions of the PIN diode; removing the first and the second sacrificial materials, and filling both the wide and the narrow sets of trenches with the same conductive material in contact with the diffused p and n regions.
摘要翻译： 通过在半导体衬底中同时蚀刻两组沟槽形成沟槽型PIN光电检测器，宽沟槽的宽度是窄沟槽的两倍以上的加工余量; 用掺杂有第一掺杂剂的牺牲材料保形地填充两种类型的沟槽，并且具有略大于窄沟槽宽度的一半的第一厚度，使得宽沟槽具有剩余的中心孔径; 在去除第一厚度的蚀刻中从宽的沟槽剥离牺牲材料，从而排空宽的沟槽; a）用相反极性的第二牺牲材料填充宽的沟槽; 或b）通过气相掺杂，等离子体掺杂，离子注入，液相掺杂，浸渍掺杂和等离子体浸入离子注入等方式，从环境中掺杂宽沟槽; 将掺杂剂扩散到衬底中，形成PIN二极管的p区和n区; 去除第一和第二牺牲材料，并用与扩散的p和n区域接触的相同导电材料填充宽和窄的沟槽组。
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公开(公告)号：US20060292789A1
公开(公告)日：2006-12-28
申请号：US11468543
申请日：2006-08-30
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L21/3081 , H01L27/10864 , H01L27/10867 , H01L27/1087
摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.
摘要翻译： 提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。
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公开(公告)号：US20060124936A1
公开(公告)日：2006-06-15
申请号：US10905002
申请日：2004-12-09
IPC分类号： H01L29/786 , H01L21/8242
CPC分类号： H01L29/78642 , H01L27/10864 , H01L27/1087
摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的键合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。
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公开(公告)号：US20050282393A1
公开(公告)日：2005-12-22
申请号：US10710061
申请日：2004-06-16
IPC分类号： H01L21/302 , H01L21/308 , H01L21/8242
CPC分类号： H01L21/3081 , H01L27/10864 , H01L27/10867 , H01L27/1087
摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.
摘要翻译： 提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。
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